PNGE 200 Project #2 S2017 Draw the wellbore schematic and arrange the following sequence of events(1 thru 10) in the order they would occur when drilling and completing a well with the following parameters and calculate # sacks, mud wt., volume and pressure where indicated using the Baker Tech Facts Engineering Handbook(Use back of this sheet for the wellbore schematic and calculations) 11 3/4″ Surface Casing set at 500 ft 7″ 26 #/ft Intermediate Casing Set at 3200 ft 4 1/2″ 13.5#/ft P-110 Production Casing set at 14100 ft Fracture Gradient 0.770 psi/ft Pore pressure 0.470 psi/ft 4 1/2 capacity bbls/ft Volume between 4 1/2 csg and 6 1/4″ hole bbls/ft Class A cement Yield (1.18 ft3/sk) _______MIRU Drilling Rig _______Calculate _______# of sacks to cement production casing back to 8200 ft in 6 1/4″ hole sz _______Run production 4 ½” casing _______Weight up mud to ______ ppg and circulate kick out of well @ 8000 ft _______Perforate production casing for lower stage _______Displace Prod casing cement volume with ____ bbls freshwater _______Set Wellhead assembly _______Fracture lower stage @ 12620 ft with _______ psi pressure _______Pick up Kelly and drill Rathole _______Run Openhole logs to determine reservoir properties Can the well be fraced with the 4 1/2″ 13.5 #/ft P-110 casing with 20% safety factor? YES / NO (Show work and explain results)

PNGE 200 Project #2 S2017 Draw the wellbore schematic and arrange the following sequence of events(1 thru 10) in the order they would occur when drilling and completing a well with the following parameters and calculate # sacks, mud wt., volume and pressure where indicated using the Baker Tech Facts Engineering Handbook(Use back of this sheet for the wellbore schematic and calculations) 11 3/4″ Surface Casing set at 500 ft 7″ 26 #/ft Intermediate Casing Set at 3200 ft 4 1/2″ 13.5#/ft P-110 Production Casing set at 14100 ft Fracture Gradient 0.770 psi/ft Pore pressure 0.470 psi/ft 4 1/2 capacity bbls/ft Volume between 4 1/2 csg and 6 1/4″ hole bbls/ft Class A cement Yield (1.18 ft3/sk) _______MIRU Drilling Rig _______Calculate _______# of sacks to cement production casing back to 8200 ft in 6 1/4″ hole sz _______Run production 4 ½” casing _______Weight up mud to ______ ppg and circulate kick out of well @ 8000 ft _______Perforate production casing for lower stage _______Displace Prod casing cement volume with ____ bbls freshwater _______Set Wellhead assembly _______Fracture lower stage @ 12620 ft with _______ psi pressure _______Pick up Kelly and drill Rathole _______Run Openhole logs to determine reservoir properties Can the well be fraced with the 4 1/2″ 13.5 #/ft P-110 casing with 20% safety factor? YES / NO (Show work and explain results)

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Programming Assignment 7: Poker (5-Card Draw) II. Prerequisites: Before starting this programming assignment, participants should be able to: Apply and implement pointers in C Pass output parameters to functions Analyze a basic set of requirements and apply top-down design principles for a problem Apply repetition structures within an algorithm Construct while (), for (), or do-while () loops in C Compose C programs consisting of sequential, conditional, and iterative statements Eliminate redundancy within a program by applying loops and functions Create structure charts for a given problem Open and close files Read, write to, and update files Manipulate file handles Apply standard library functions: fopen (), fclose (), fscanf (), and fprintf () Apply and implement pointers 2-dimenional arrays Define and apply structs in C Compose decision statements (“if” conditional statements) Create and utilize compound conditions Summarize topics from Hanly & Koffman Chapter 8 including: What is an array? Distinguishing between single dimensional and 2-dimentional arrays What is an index? III. Overview & Requirements: Write a program that allows a user to play 5-Card-Draw Poker against the computer. Start with the following example code supplied by Deitel & Deitel (example code). This will help you get started with the game of Poker. Please read this site to learn the rules of Poker http://en.wikipedia.org/wiki/5_card_draw. Complete the following step and you will have a working Poker game!!! Adapted from Deitel & Deitel’s C How to Program (6th Edition): (1) In order to complete the game of 5-card-draw poker, you should complete the following functions: (a) (5 pts) Modify the card dealing function provided in the example code so that a five-card poker hand is dealt. (b) (5 pts) Write a function to determine if the hand contains a pair. (c) (5 pts) Write a function to determine if the hand contains two pairs. (d) (5 pts) Write a function to determine if the hand contains three of a kind (e.g. three jacks). (e) (5 pts) Write a function to determine if the hand contains four of a kind (e.g. four aces). (f) (5 pts) Write a function to determine if the hand contains a flush (i.e. all five cards of the same suit). (g) (5 pts) Write a function to determine if the hand contains a straight (i.e. five cards of consecutive face values). (2) (20 pts) Use the functions developed in (1) to deal two five-card poker hands, evaluate each hand, and determine which is the better hand. (3) (25 pts) Simulate the dealer. The dealer’s five-card hand is dealt “face down” so the player cannot see it. The program should then evaluate the dealer’s hand, and based on the quality of the hand, the dealer should draw one, two, or three more cards to replace the corresponding number of unneeded cards in the original hand. The program should then re-evaluate the dealer’s hand. (4) (10 pts) Make the program handle the dealer’s five-card hand automatically. The player should be allowed to decide which cards of the player’s hand to replace. The program should then evaluate both hands and determine who wins. Now use the program to play 10 games against the computer. You should be able to test and modify or refine your Poker game based on these results!

Programming Assignment 7: Poker (5-Card Draw) II. Prerequisites: Before starting this programming assignment, participants should be able to: Apply and implement pointers in C Pass output parameters to functions Analyze a basic set of requirements and apply top-down design principles for a problem Apply repetition structures within an algorithm Construct while (), for (), or do-while () loops in C Compose C programs consisting of sequential, conditional, and iterative statements Eliminate redundancy within a program by applying loops and functions Create structure charts for a given problem Open and close files Read, write to, and update files Manipulate file handles Apply standard library functions: fopen (), fclose (), fscanf (), and fprintf () Apply and implement pointers 2-dimenional arrays Define and apply structs in C Compose decision statements (“if” conditional statements) Create and utilize compound conditions Summarize topics from Hanly & Koffman Chapter 8 including: What is an array? Distinguishing between single dimensional and 2-dimentional arrays What is an index? III. Overview & Requirements: Write a program that allows a user to play 5-Card-Draw Poker against the computer. Start with the following example code supplied by Deitel & Deitel (example code). This will help you get started with the game of Poker. Please read this site to learn the rules of Poker http://en.wikipedia.org/wiki/5_card_draw. Complete the following step and you will have a working Poker game!!! Adapted from Deitel & Deitel’s C How to Program (6th Edition): (1) In order to complete the game of 5-card-draw poker, you should complete the following functions: (a) (5 pts) Modify the card dealing function provided in the example code so that a five-card poker hand is dealt. (b) (5 pts) Write a function to determine if the hand contains a pair. (c) (5 pts) Write a function to determine if the hand contains two pairs. (d) (5 pts) Write a function to determine if the hand contains three of a kind (e.g. three jacks). (e) (5 pts) Write a function to determine if the hand contains four of a kind (e.g. four aces). (f) (5 pts) Write a function to determine if the hand contains a flush (i.e. all five cards of the same suit). (g) (5 pts) Write a function to determine if the hand contains a straight (i.e. five cards of consecutive face values). (2) (20 pts) Use the functions developed in (1) to deal two five-card poker hands, evaluate each hand, and determine which is the better hand. (3) (25 pts) Simulate the dealer. The dealer’s five-card hand is dealt “face down” so the player cannot see it. The program should then evaluate the dealer’s hand, and based on the quality of the hand, the dealer should draw one, two, or three more cards to replace the corresponding number of unneeded cards in the original hand. The program should then re-evaluate the dealer’s hand. (4) (10 pts) Make the program handle the dealer’s five-card hand automatically. The player should be allowed to decide which cards of the player’s hand to replace. The program should then evaluate both hands and determine who wins. Now use the program to play 10 games against the computer. You should be able to test and modify or refine your Poker game based on these results!

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Lab Description: Follow the instructions in the lab tasks below to complete Problems 3 and 4 of Project 10 from the Digilent Real Digital website. These are two design problems involving finite state machine design and interfacing with seven-segment display. First start by analyzing the block diagram for Problem 3 of Project 10. Then, use VHDL to design each of the system components. You will need to use four separate design modules and instantiate each of these within a fifth design module for the overall system. For Problem 4 of Project 10, carefully read through the problem and the “Seven-Segment Display” section of the FPGA board’s user guide before carefully planning the design of this system. Lab Tasks: 1. Complete Problem 3 of Project 10 (a single-digit stopwatch): a. Pay particular attention to the block diagram displayed for this problem. Create each of the four components to this system: i. Seven-segment decoder: You will be able to reuse your design from Lab 2 ii. 4-bit counter: I recommend taking a look at the behavior binary counter illustrated in “Binary counters in VHDL” from Module 10 iii. Clock divider: You will be able to reuse your design from Lab 5. However, you will have to revise this design for task 2. For more information, I recommend taking a look at “Binary counters in VHDL” from Module 10 for information about clock dividers. Note: The stopwatch circuit will increment the digit once every second. Design your clock divider accordingly in order to meet this timing specification. Remember, the clock on the lab FPGA board (Spartan 3) has a frequency of 50 MHz. If you purchased your board, the FPGA Basys 3 or Nexys 4 DDR FPGA board has a frequency of 100 MHz. iv. Controller: This is the main component you will design using a finite state machine b. Use VHDL test benches to verify the correct operation of your 4-bit counter, clock divider (I suggest you use a small divider value for simulating so you do not have to simulate for a long duration), controller, and overall system (again, I suggest you use a small divider value for simulating) c. Ask the instructor to check your designs, simulation waveforms, and FPGA board implementation for your circuit 2. Complete Problem 4 of Project 10 (a multi-digit stopwatch): a. Note: The least-significant digit should change at a rate of once per millisecond. However, for our design, the most-significant bit will not change once per second since each digit will count from 0-F. b. For more information about the timing and pinouts of the seven-segment display, please refer to your board’s user guide from Digilent’s website. Or use this direct link to our lab’s Spartan 3 FPGA board’s user guide. Look for a heading named “Seven-Segment Display” for more information about the timing requirements. c. Use VHDL test benches to verify the correct operation of your system and its components (again, I suggest you use a small divider value for simulating) d. Ask the instructor to check your designs, simulation waveforms, and FPGA board implementation for your circuit 3. If you complete both of the tasks above, then you may continue and complete one or both of the following extra credit tasks: a. Decimal, Multi-Digit Stopwatch (extra credit task) You may complete this extra credit task instead of the hexadecimal, multi-digit stopwatch (lab task 2), or you may complete lab task 2 first, then complete this task i. Modify/create a multi-digit stopwatch so that only decimal numbers are displayed. The least-significant digit should change at a rate of once per millisecond and the most-significant bit will change once per second. This will now act like a real stopwatch. ii. Use VHDL test benches to verify the correct operation of your system and its components (again, I suggest you use a small divider value for simulating) iii. Ask the instructor to check your designs, simulation waveforms, and FPGA board implementation for your circuit iv. Answer the extra credit lab task A questions on the cover sheet. In addition, list any references you use for this extra credit task. b. A Blinking, Multi-Digit Stopwatch (extra credit task) You may complete this extra credit task by altering your design of the hexadecimal or decimal multidigit stopwatch i. Modify your multi-digit stopwatch so the seven-segment display will blink rapidly once the most-significant digit is 9 or greater (to signal the stopwatch is close to the maximum value). This is your chance to design the system you described in the discussion question on the cover sheet. You may choose an appropriate rate at which the seven-segment display will blink. ii. Use VHDL test benches to verify the correct operation of your system and its components (again, I suggest you use a small divider value for simulating) iii. Ask the instructor to check your designs, simulation waveforms, and FPGA board implementation for your circuit iv. Answer the extra credit lab task B questions on the cover sheet. In addition, list any references you use for this extra credit task.

Lab Description: Follow the instructions in the lab tasks below to complete Problems 3 and 4 of Project 10 from the Digilent Real Digital website. These are two design problems involving finite state machine design and interfacing with seven-segment display. First start by analyzing the block diagram for Problem 3 of Project 10. Then, use VHDL to design each of the system components. You will need to use four separate design modules and instantiate each of these within a fifth design module for the overall system. For Problem 4 of Project 10, carefully read through the problem and the “Seven-Segment Display” section of the FPGA board’s user guide before carefully planning the design of this system. Lab Tasks: 1. Complete Problem 3 of Project 10 (a single-digit stopwatch): a. Pay particular attention to the block diagram displayed for this problem. Create each of the four components to this system: i. Seven-segment decoder: You will be able to reuse your design from Lab 2 ii. 4-bit counter: I recommend taking a look at the behavior binary counter illustrated in “Binary counters in VHDL” from Module 10 iii. Clock divider: You will be able to reuse your design from Lab 5. However, you will have to revise this design for task 2. For more information, I recommend taking a look at “Binary counters in VHDL” from Module 10 for information about clock dividers. Note: The stopwatch circuit will increment the digit once every second. Design your clock divider accordingly in order to meet this timing specification. Remember, the clock on the lab FPGA board (Spartan 3) has a frequency of 50 MHz. If you purchased your board, the FPGA Basys 3 or Nexys 4 DDR FPGA board has a frequency of 100 MHz. iv. Controller: This is the main component you will design using a finite state machine b. Use VHDL test benches to verify the correct operation of your 4-bit counter, clock divider (I suggest you use a small divider value for simulating so you do not have to simulate for a long duration), controller, and overall system (again, I suggest you use a small divider value for simulating) c. Ask the instructor to check your designs, simulation waveforms, and FPGA board implementation for your circuit 2. Complete Problem 4 of Project 10 (a multi-digit stopwatch): a. Note: The least-significant digit should change at a rate of once per millisecond. However, for our design, the most-significant bit will not change once per second since each digit will count from 0-F. b. For more information about the timing and pinouts of the seven-segment display, please refer to your board’s user guide from Digilent’s website. Or use this direct link to our lab’s Spartan 3 FPGA board’s user guide. Look for a heading named “Seven-Segment Display” for more information about the timing requirements. c. Use VHDL test benches to verify the correct operation of your system and its components (again, I suggest you use a small divider value for simulating) d. Ask the instructor to check your designs, simulation waveforms, and FPGA board implementation for your circuit 3. If you complete both of the tasks above, then you may continue and complete one or both of the following extra credit tasks: a. Decimal, Multi-Digit Stopwatch (extra credit task) You may complete this extra credit task instead of the hexadecimal, multi-digit stopwatch (lab task 2), or you may complete lab task 2 first, then complete this task i. Modify/create a multi-digit stopwatch so that only decimal numbers are displayed. The least-significant digit should change at a rate of once per millisecond and the most-significant bit will change once per second. This will now act like a real stopwatch. ii. Use VHDL test benches to verify the correct operation of your system and its components (again, I suggest you use a small divider value for simulating) iii. Ask the instructor to check your designs, simulation waveforms, and FPGA board implementation for your circuit iv. Answer the extra credit lab task A questions on the cover sheet. In addition, list any references you use for this extra credit task. b. A Blinking, Multi-Digit Stopwatch (extra credit task) You may complete this extra credit task by altering your design of the hexadecimal or decimal multidigit stopwatch i. Modify your multi-digit stopwatch so the seven-segment display will blink rapidly once the most-significant digit is 9 or greater (to signal the stopwatch is close to the maximum value). This is your chance to design the system you described in the discussion question on the cover sheet. You may choose an appropriate rate at which the seven-segment display will blink. ii. Use VHDL test benches to verify the correct operation of your system and its components (again, I suggest you use a small divider value for simulating) iii. Ask the instructor to check your designs, simulation waveforms, and FPGA board implementation for your circuit iv. Answer the extra credit lab task B questions on the cover sheet. In addition, list any references you use for this extra credit task.

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Lab Description: Follow the instructions in the lab tasks below to complete Problems 1 through 4. These problems will guide you in observing signal delays and timing hazards of logic circuits (both Sum-of-Products (SOP) and Product-of-Sums (POS) circuits). These problems will also guide you in adding circuitry to eliminate a timing hazard. Use VHDL to design the circuits. Carefully follow the directions provided in the lab tasks below. Write your answers to the questions asked by the problems. Do not print out the VHDL code and waveforms as asked by the problems, instead include these on the cover sheet for this lab and print this out when you are done. Do not worry about annotating or putting arrows/notes on the waveforms–just make sure any signals or transitions of interest are shown in your screenshot. For each problem, use VHDL assignment statements for each gate of the Boolean expression. You must add delay for each gate and inverter as described by the problem. Do this by using the “after” statement: Z <= (A and B) after 1 ns; Refer to Digilent Real Digital Module 8 for more information about the "after" statement. Lab Tasks: 1. Complete Problem 1 of Project 8. Simulate all input combinations for this SOP (Sum-of-Products) expression. However, be aware that specific input sequences are required to observe a timing hazard. The problem states that you will need to observe the output when B and C are both high (logic 1) and A transitions from high to low to high (logic 1 to 0, then back to 1). 2. Complete Problem 4 of Project 8. Increase the delay of the OR gate as specified and re-simulate to answer the questions. 3. Complete Problem 2 of Project 8. Change the delay of the OR gate back to the 1 ns that you used for Problem 1. Add the new logic gate (with delay) to your VHDL for the SOP expression and re-simulate to answer the questions. 4. Complete Problem 3 of Project 8. You may create any POS (Product-of-Sums) expression for this problem, however, not all POS expressions will have a timing hazard (so spend some time thinking about how a timing hazard can be generated with a POS expression). Once again, simulate all input combinations for your POS expression but be aware that specific input sequences are required to observe a timing hazard. For this problem, you will also add the new logic gate (with delay) to your VHDL for your POS expression in order to eliminate the timing hazard; you will need to re-simulate with this additional logic gate in order to answer the questions. Problem 1. Implement the function Y = A’.B + A.C in the VHDL tool. Define the INV, OR and two AND operations separately, and give each operation a 1ns delay. Simulate the circuit with all possible combinations of inputs. Watch all circuit nets (inputs, outputs, and intermediate nets) during the simulation. Answer the questions below. Observe the outputs of the AND gates and the overall circuit output when B and C are both high, and A transitions from H to L and then from L to H (you may want to create another simulation to focus on this behavior). What output behavior do you notice when A transitions? What happens when A transitions and B or C are held a ‘0’? How long is the output glitch? _______ Is it positive ( ) or negative ( ) (circle one)? Change the delay through the inverter to 2ns, and resimulate. Now how long is output glitch? ______ What can you say about the relationship between the inverter gate delay and the length of the timing glitch? Based on this simple experiment, an SOP circuit can exhibit positive/negative glitches (circle one) when an input that arrives at one AND gate in a complemented form and another AND gate in uncomplemented form transitions from a _____ to a _____. Problem 2. Enter the logic equation from problem 1 in the K-map below, and loop the equation with redundant term included. Add the redundant term to the Xilinx circuit, re-simulate, and answer the questions. B C A 00 01 11 10 0 1 F Did adding the new gate to the circuit change the logical behavior of the circuit? What effect did the new gate have on the output, particularly when A changes and B and C are both held high? Problem 3. Create a three-input POS circuit to illustrate the formation of a glitch. Drive the simulator to illustrate a glitch in the POS circuit, and answer the questions below. A POS circuit can exhibit a positive/negative glitch (circle one) when an input that arrives at one OR gate in a complemented form and another OR gate in un-complemented form transitions from a _____ to a _____. Write the POS equation you used to show the glitch: Enter the equation in the K-map below, loop the original equation with the redundant term, add the redundant gate to your Xilinx circuit, and resimulate. How did adding the new gate to the circuit change the logical behavior of the circuit? What effect did the new gate have on the output, particularly when A changes and B and C are both held high? Print and submit the circuits and simulation output, label the output glitches in the simulation output, and draw arrows on the simulation output between the events that caused the glitches (i.e., a transition in an input signal) and the glitches themselves. Problem 4. Copy the SOP circuit above to a new VHDL file, and increase the delay of the output OR gate. Simulate the circuit and answer the questions below. How did adding delay to the output gate change the output transition? Does adding delay to the output gate change the circuit’s glitch behavior in any way? Name: Signal Delays Date: Designing with VHDL Grade Item Grade Five segments of VHDL Code for Problems 1-4: /10 Five simulation screenshots for Problems 1-4: /10 Questions from Problems 1-4: /16 Total Grade: /36 VHDL Code: Copy-paste your VHDL design code (just the code you wrote) for: • The SOP expression with the timing hazard (Problem 1, Project 8): • The SOP expression with increased OR gate delay (Problem 4, Project 8): • The SOP expression with the extra logic gate in order to eliminate the timing hazard (Problem 2, Project 8): • Your POS expression with the timing hazard (Problem 3, Project 8): • Your POS expression with the extra logic gate in order to eliminate the timing hazard (Problem 3, Project 8): Simulation Screenshots: Use the “Print Screen” button to capture your screenshot (it should show the entire screen, not just the window of the program). • The SOP expression with the timing hazard (Problem 1, Project 8): • The SOP expression with increased OR gate delay (Problem 4, Project 8): • The SOP expression with the extra logic gate in order to eliminate the timing hazard (Problem 2, Project 8): • Your POS expression with the timing hazard (Problem 3, Project 8): • Your POS expression with the extra logic gate in order to eliminate the timing hazard (Problem 3, Project 8): Simulation Screenshot Tips: (you can delete this once you capture your screenshot) 1. Make the “Wave” window large by clicking the “+” button near the upper-right of the window 2. Click the “Zoom Full” button (looks like a blue/green-filled magnifying glass) to enlarge your waveforms 3. In order to not print a lot of black, change the color scheme of the “Wave” window: 3.1. Click ToolsEdit Preferences… 3.2. The “By Window” tab should be selected, then click Wave Windows in the “Window List” to the left 3.3. Scroll to the bottom of the “Wave Windows Color Scheme” list and click waveBackground. Then click white in the color “Palette” at the right of the screen. 3.4. Now color the waveforms and text black: 3.4.1. Click LOGIC_0 in the “Wave Windows Color Scheme.” Then click black in the color “Palette” at the right of the screen. 3.4.2. Repeat this for LOGIC_1, timeColor, and cursorColor (if you have a cursor you want to print) 3.5. Once you have captured your screenshot, you can click the Reset Defaults button to restore the “Wave” window to its original color scheme Questions: (Please use this cover sheet to type and print your responses) 1. List the references you used for this lab assignment (e.g. sources/websites used or students with whom you discussed this assignment) 2. Do you have any comments or suggestions for this lab exercise?

Lab Description: Follow the instructions in the lab tasks below to complete Problems 1 through 4. These problems will guide you in observing signal delays and timing hazards of logic circuits (both Sum-of-Products (SOP) and Product-of-Sums (POS) circuits). These problems will also guide you in adding circuitry to eliminate a timing hazard. Use VHDL to design the circuits. Carefully follow the directions provided in the lab tasks below. Write your answers to the questions asked by the problems. Do not print out the VHDL code and waveforms as asked by the problems, instead include these on the cover sheet for this lab and print this out when you are done. Do not worry about annotating or putting arrows/notes on the waveforms–just make sure any signals or transitions of interest are shown in your screenshot. For each problem, use VHDL assignment statements for each gate of the Boolean expression. You must add delay for each gate and inverter as described by the problem. Do this by using the “after” statement: Z <= (A and B) after 1 ns; Refer to Digilent Real Digital Module 8 for more information about the "after" statement. Lab Tasks: 1. Complete Problem 1 of Project 8. Simulate all input combinations for this SOP (Sum-of-Products) expression. However, be aware that specific input sequences are required to observe a timing hazard. The problem states that you will need to observe the output when B and C are both high (logic 1) and A transitions from high to low to high (logic 1 to 0, then back to 1). 2. Complete Problem 4 of Project 8. Increase the delay of the OR gate as specified and re-simulate to answer the questions. 3. Complete Problem 2 of Project 8. Change the delay of the OR gate back to the 1 ns that you used for Problem 1. Add the new logic gate (with delay) to your VHDL for the SOP expression and re-simulate to answer the questions. 4. Complete Problem 3 of Project 8. You may create any POS (Product-of-Sums) expression for this problem, however, not all POS expressions will have a timing hazard (so spend some time thinking about how a timing hazard can be generated with a POS expression). Once again, simulate all input combinations for your POS expression but be aware that specific input sequences are required to observe a timing hazard. For this problem, you will also add the new logic gate (with delay) to your VHDL for your POS expression in order to eliminate the timing hazard; you will need to re-simulate with this additional logic gate in order to answer the questions. Problem 1. Implement the function Y = A’.B + A.C in the VHDL tool. Define the INV, OR and two AND operations separately, and give each operation a 1ns delay. Simulate the circuit with all possible combinations of inputs. Watch all circuit nets (inputs, outputs, and intermediate nets) during the simulation. Answer the questions below. Observe the outputs of the AND gates and the overall circuit output when B and C are both high, and A transitions from H to L and then from L to H (you may want to create another simulation to focus on this behavior). What output behavior do you notice when A transitions? What happens when A transitions and B or C are held a ‘0’? How long is the output glitch? _______ Is it positive ( ) or negative ( ) (circle one)? Change the delay through the inverter to 2ns, and resimulate. Now how long is output glitch? ______ What can you say about the relationship between the inverter gate delay and the length of the timing glitch? Based on this simple experiment, an SOP circuit can exhibit positive/negative glitches (circle one) when an input that arrives at one AND gate in a complemented form and another AND gate in uncomplemented form transitions from a _____ to a _____. Problem 2. Enter the logic equation from problem 1 in the K-map below, and loop the equation with redundant term included. Add the redundant term to the Xilinx circuit, re-simulate, and answer the questions. B C A 00 01 11 10 0 1 F Did adding the new gate to the circuit change the logical behavior of the circuit? What effect did the new gate have on the output, particularly when A changes and B and C are both held high? Problem 3. Create a three-input POS circuit to illustrate the formation of a glitch. Drive the simulator to illustrate a glitch in the POS circuit, and answer the questions below. A POS circuit can exhibit a positive/negative glitch (circle one) when an input that arrives at one OR gate in a complemented form and another OR gate in un-complemented form transitions from a _____ to a _____. Write the POS equation you used to show the glitch: Enter the equation in the K-map below, loop the original equation with the redundant term, add the redundant gate to your Xilinx circuit, and resimulate. How did adding the new gate to the circuit change the logical behavior of the circuit? What effect did the new gate have on the output, particularly when A changes and B and C are both held high? Print and submit the circuits and simulation output, label the output glitches in the simulation output, and draw arrows on the simulation output between the events that caused the glitches (i.e., a transition in an input signal) and the glitches themselves. Problem 4. Copy the SOP circuit above to a new VHDL file, and increase the delay of the output OR gate. Simulate the circuit and answer the questions below. How did adding delay to the output gate change the output transition? Does adding delay to the output gate change the circuit’s glitch behavior in any way? Name: Signal Delays Date: Designing with VHDL Grade Item Grade Five segments of VHDL Code for Problems 1-4: /10 Five simulation screenshots for Problems 1-4: /10 Questions from Problems 1-4: /16 Total Grade: /36 VHDL Code: Copy-paste your VHDL design code (just the code you wrote) for: • The SOP expression with the timing hazard (Problem 1, Project 8): • The SOP expression with increased OR gate delay (Problem 4, Project 8): • The SOP expression with the extra logic gate in order to eliminate the timing hazard (Problem 2, Project 8): • Your POS expression with the timing hazard (Problem 3, Project 8): • Your POS expression with the extra logic gate in order to eliminate the timing hazard (Problem 3, Project 8): Simulation Screenshots: Use the “Print Screen” button to capture your screenshot (it should show the entire screen, not just the window of the program). • The SOP expression with the timing hazard (Problem 1, Project 8): • The SOP expression with increased OR gate delay (Problem 4, Project 8): • The SOP expression with the extra logic gate in order to eliminate the timing hazard (Problem 2, Project 8): • Your POS expression with the timing hazard (Problem 3, Project 8): • Your POS expression with the extra logic gate in order to eliminate the timing hazard (Problem 3, Project 8): Simulation Screenshot Tips: (you can delete this once you capture your screenshot) 1. Make the “Wave” window large by clicking the “+” button near the upper-right of the window 2. Click the “Zoom Full” button (looks like a blue/green-filled magnifying glass) to enlarge your waveforms 3. In order to not print a lot of black, change the color scheme of the “Wave” window: 3.1. Click ToolsEdit Preferences… 3.2. The “By Window” tab should be selected, then click Wave Windows in the “Window List” to the left 3.3. Scroll to the bottom of the “Wave Windows Color Scheme” list and click waveBackground. Then click white in the color “Palette” at the right of the screen. 3.4. Now color the waveforms and text black: 3.4.1. Click LOGIC_0 in the “Wave Windows Color Scheme.” Then click black in the color “Palette” at the right of the screen. 3.4.2. Repeat this for LOGIC_1, timeColor, and cursorColor (if you have a cursor you want to print) 3.5. Once you have captured your screenshot, you can click the Reset Defaults button to restore the “Wave” window to its original color scheme Questions: (Please use this cover sheet to type and print your responses) 1. List the references you used for this lab assignment (e.g. sources/websites used or students with whom you discussed this assignment) 2. Do you have any comments or suggestions for this lab exercise?

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Lab Description: Follow the instructions in the lab tasks below to behaviorially create and simulate a flip-flop. Afterwards, you will create a register and Arithmetic Logic Unit (ALU). Refer to Module 7 from the Digilent Real Digital website for more information about ALUs. These two components are the main components required to create an accumulator datapath. This accumulator datapath will act like a simple processor; the ALU will execute simple arithmetic/logic operations and each result will be stored in the register. In an accumulator, the value of the register will be upedated with each operation; the register is used as an input to the ALU and the newly computed result of the operation will be stored back into the register. You will create and implement this accumulator datapath in the last task of this lab. However, you will need to add an additional component to enable it to clearly operate on the FPGA board. You will create and use a clock divider to create a slower version of the FPGA board’s clock when you implement the accumulator datapath on the FPGA board. Refer to Module 10 from the Digilent Real Digital website for more information about clock dividers. Lab Tasks: 1. Create a behavioral VHDL module for a Rising-Edge Triggered (RET) D-Flip-Flop (DFF): a. In your design, use inputs “D” (data), “CLK” (the clock), “RST” (an asynchronous reset), “SET” (a synchronous set or preset signal), “CE” (clock enable), and output “Q” b. Create a VHDL test bench and simulate the flip-flop. Be sure to show the following behaviors with your simulation: i. The output “Q” sampling a ‘0’ from the input “D” ii. The output “Q” sampling a ‘1’ from the input “D” iii. The correct operation of the asynchronous reset iv. The correct operation of the synchronous preset v. The correct operation of the clock enable c. Include a screenshot of your simulation on the lab’s cover sheet. Label each of these behaviors on the waveform (it is ok to print out your cover sheet and write each behavior on the waveform). 2. Create a behavioral VHDL module for a 4-bit Arithmetic Logic Unit (ALU): a. I suggest you refer to Module 7 from the Digilent Real Digital website (in particular, the sections about ALU circuits and behavioral VHDL ALU descriptions). This 4-bit ALU will calculate arithmetic and logical expressions on two 4-bit numbers. Use behavioral expressions for the arithmetic and logic expressions (do not use port map statements to create a structural design using your ripple-carry adder from lab 3). Assume that the select input (or opcode) is 2-bits and is defined as shown in the table below: Opcode Function 00 A 01 A plus 1 10 A plus B 11 A and B b. Create a VHDL test bench to test your ALU. Use two input signal (the 4-bit values for A and B) combinations to test each operation of the ALU. Simulate your design and verify your output. Include a screenshot of your simulation on the lab’s cover sheet. 3. Create an accumulator datapath: a. First, create a 4-bit register. This is very similar to your flip-flop design from lab task 1. Ensure that your 4-bit register has inputs “D” (data), “CLK” (the clock), and “RST” (an asynchronous reset), and an output “Q”. Create a test bench and ensure that your 4-bit register operates correctly. b. Next, create a design module for the accumulator datapath and import your 4-bit register, 4-bit ALU, and seven-sgement display decoder (from lab 2) as components to this system. Connect your register, ALU, and seven-segment display decoder as follows: i. Connect the output of your ALU to the “D” input of your register ii. Connect the “Q” output of your register to both the “A” input of your ALU and the input of your seven-segement display iii. You should be left with four overall inputs: the “B” input of your ALU, the opcode input of your ALU, the CLK, and RST iv. You should be left with one overall output: the seven-segment display output c. Create a test bench to simulate the behavior of your accumulator datapath. In your test bench, simulate a few clock cycles to verify the correct operation of your system. d. Before implementing this system on the FPGA board, create and add one additional component to your system. Create and add a clock divider to this system; the input will be the board’s clock and the output will be a slower version of the clock to use for the register. Design your clock divider to slow the clock frequency to 1 Hz (1 clock cycle per second). Note that the clock on the lab FPGA board (Spartan 3) has a frequency of 50 MHz. If you purchased your board, the FPGA Basys 3 or Nexys 4 DDR FPGA board has a frequency of 100 MHz. I highly recommend taking a look at “Binary counters in VHDL” from Module 10 from the Digilent Real Digital website for information about clock dividers. e. Now, implement this system on the FPGA board. Connect the data input to four switches, connect the ALU opcode inputs to two buttons, the RST signal to one button, the CLK signal to the board’s clock, and the seven-segment display output to the seven-segment display. f. Ask the instructor to check your design, simulation waveforms, and FPGA board implementation of your circuit

Lab Description: Follow the instructions in the lab tasks below to behaviorially create and simulate a flip-flop. Afterwards, you will create a register and Arithmetic Logic Unit (ALU). Refer to Module 7 from the Digilent Real Digital website for more information about ALUs. These two components are the main components required to create an accumulator datapath. This accumulator datapath will act like a simple processor; the ALU will execute simple arithmetic/logic operations and each result will be stored in the register. In an accumulator, the value of the register will be upedated with each operation; the register is used as an input to the ALU and the newly computed result of the operation will be stored back into the register. You will create and implement this accumulator datapath in the last task of this lab. However, you will need to add an additional component to enable it to clearly operate on the FPGA board. You will create and use a clock divider to create a slower version of the FPGA board’s clock when you implement the accumulator datapath on the FPGA board. Refer to Module 10 from the Digilent Real Digital website for more information about clock dividers. Lab Tasks: 1. Create a behavioral VHDL module for a Rising-Edge Triggered (RET) D-Flip-Flop (DFF): a. In your design, use inputs “D” (data), “CLK” (the clock), “RST” (an asynchronous reset), “SET” (a synchronous set or preset signal), “CE” (clock enable), and output “Q” b. Create a VHDL test bench and simulate the flip-flop. Be sure to show the following behaviors with your simulation: i. The output “Q” sampling a ‘0’ from the input “D” ii. The output “Q” sampling a ‘1’ from the input “D” iii. The correct operation of the asynchronous reset iv. The correct operation of the synchronous preset v. The correct operation of the clock enable c. Include a screenshot of your simulation on the lab’s cover sheet. Label each of these behaviors on the waveform (it is ok to print out your cover sheet and write each behavior on the waveform). 2. Create a behavioral VHDL module for a 4-bit Arithmetic Logic Unit (ALU): a. I suggest you refer to Module 7 from the Digilent Real Digital website (in particular, the sections about ALU circuits and behavioral VHDL ALU descriptions). This 4-bit ALU will calculate arithmetic and logical expressions on two 4-bit numbers. Use behavioral expressions for the arithmetic and logic expressions (do not use port map statements to create a structural design using your ripple-carry adder from lab 3). Assume that the select input (or opcode) is 2-bits and is defined as shown in the table below: Opcode Function 00 A 01 A plus 1 10 A plus B 11 A and B b. Create a VHDL test bench to test your ALU. Use two input signal (the 4-bit values for A and B) combinations to test each operation of the ALU. Simulate your design and verify your output. Include a screenshot of your simulation on the lab’s cover sheet. 3. Create an accumulator datapath: a. First, create a 4-bit register. This is very similar to your flip-flop design from lab task 1. Ensure that your 4-bit register has inputs “D” (data), “CLK” (the clock), and “RST” (an asynchronous reset), and an output “Q”. Create a test bench and ensure that your 4-bit register operates correctly. b. Next, create a design module for the accumulator datapath and import your 4-bit register, 4-bit ALU, and seven-sgement display decoder (from lab 2) as components to this system. Connect your register, ALU, and seven-segment display decoder as follows: i. Connect the output of your ALU to the “D” input of your register ii. Connect the “Q” output of your register to both the “A” input of your ALU and the input of your seven-segement display iii. You should be left with four overall inputs: the “B” input of your ALU, the opcode input of your ALU, the CLK, and RST iv. You should be left with one overall output: the seven-segment display output c. Create a test bench to simulate the behavior of your accumulator datapath. In your test bench, simulate a few clock cycles to verify the correct operation of your system. d. Before implementing this system on the FPGA board, create and add one additional component to your system. Create and add a clock divider to this system; the input will be the board’s clock and the output will be a slower version of the clock to use for the register. Design your clock divider to slow the clock frequency to 1 Hz (1 clock cycle per second). Note that the clock on the lab FPGA board (Spartan 3) has a frequency of 50 MHz. If you purchased your board, the FPGA Basys 3 or Nexys 4 DDR FPGA board has a frequency of 100 MHz. I highly recommend taking a look at “Binary counters in VHDL” from Module 10 from the Digilent Real Digital website for information about clock dividers. e. Now, implement this system on the FPGA board. Connect the data input to four switches, connect the ALU opcode inputs to two buttons, the RST signal to one button, the CLK signal to the board’s clock, and the seven-segment display output to the seven-segment display. f. Ask the instructor to check your design, simulation waveforms, and FPGA board implementation of your circuit

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Advertising and Critical Analysis For this essay you will examine a selection of commercials. This essay will require that you engage in some in-depth examination of 3-4 commercials. This “close viewing” of the commercials should lead you to a thesis that answers a question such as “Who do the advertisers think that I am?” or “What do these commercials say about us?” You need to do more than simply list some commercials and summarize them – although it is important that you summarize the commercials so that the reader can “see” them. A strong essay will look deeper into the commercial and its product – it will go beyond what is simply stated and instead examine the tangible elements of the commercial as well as what is underlying or unspoken in the advertisement. While writing this, here are some things to consider: • Besides the actual product, what else is the ad selling or promoting? • What human instinct, desire, or shortcoming is the ad playing to? • What is used to make the sale and turn consumers into customers (humor, sex, youth, etc.)? • How do these ads work in conjunction with the show during which they are aired? • Who do you think this ad is aimed at (audience)? • Although only a short commercial, what do you think these advertisements say about American culture or the American people? Helpful hints: • Choose commercials from specific sectors or ones that deal with similar ideas (i.e. alcohol, trucks, military, disabilities, etc.). Doing this will help you come up with a tight focus and hold to your thesis throughout the essay. • This essay needs to be 5 – 6 pages of polished and delightfully insightful prose. In addition your paper needs to exhibit all the standard formatting and fonts. This essay also requires a Works Cited page carefully listing any sources referenced, including the commercials being discussed.

Advertising and Critical Analysis For this essay you will examine a selection of commercials. This essay will require that you engage in some in-depth examination of 3-4 commercials. This “close viewing” of the commercials should lead you to a thesis that answers a question such as “Who do the advertisers think that I am?” or “What do these commercials say about us?” You need to do more than simply list some commercials and summarize them – although it is important that you summarize the commercials so that the reader can “see” them. A strong essay will look deeper into the commercial and its product – it will go beyond what is simply stated and instead examine the tangible elements of the commercial as well as what is underlying or unspoken in the advertisement. While writing this, here are some things to consider: • Besides the actual product, what else is the ad selling or promoting? • What human instinct, desire, or shortcoming is the ad playing to? • What is used to make the sale and turn consumers into customers (humor, sex, youth, etc.)? • How do these ads work in conjunction with the show during which they are aired? • Who do you think this ad is aimed at (audience)? • Although only a short commercial, what do you think these advertisements say about American culture or the American people? Helpful hints: • Choose commercials from specific sectors or ones that deal with similar ideas (i.e. alcohol, trucks, military, disabilities, etc.). Doing this will help you come up with a tight focus and hold to your thesis throughout the essay. • This essay needs to be 5 – 6 pages of polished and delightfully insightful prose. In addition your paper needs to exhibit all the standard formatting and fonts. This essay also requires a Works Cited page carefully listing any sources referenced, including the commercials being discussed.

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• Section 1: Design Description (<2/3 page) o Describe your design, including a SCHEMATIC, a PHOTOGRAPH, and a description of materials/items used o Describe why you chose your design • Section 2: Analysis (only as much length as is necessary to clearly communicate your analysis). Note that scanning handwritten resistance networks may be faster/easier than creating digital figures. o Estimate the rate in Watts at which sunlight is absorbed by your design (assume a solar flux of 1000 W/m2) o Show a thermal resistance network for each heat transfer path for the heat loss from your design. Calculate/estimate all thermal resistances. For all convection correlations, list the assumed geometry, the equation being used, and the calculated ‘h’ value. o Identify the dominant mode of heat loss, and discuss why this is the case. o STATE AND JUSTIFY all assumptions and estimates in the analysis. And by “justify” I mean “PROVE to me that your assumption is reasonable” • Section 3: Reflection (<1/2 page) o Suggest TWO design modifications that would significantly reduce the heat loss from your design. One modification must be a low-­‐cost modification that would fit within your project budget, and the other modification must be a modification using commercially available materials/technologies that would be realistically used in industry (i.e. without an absurd cost constraint). Note that you will have to perform some independent research on available materials and technologies to complete this. • Section 4: Bill of Materials o List ALL materials in the design (automatic 20% grade reduction for any material I find in your design that is unaccounted for in your bill of materials) o Can treat scavenged items as zero cost only if anyone could reasonably attain them freely (for donated items you must count the full purchase cost) o For structural materials, you must use the minimum UNIT COST, not a portion cost (i.e. if you buy an item in its smallest available quantity and only use 10% of the item, you still must include the TOTAL item cost) o For fastening/assembly/filler materials, you may use portion costs (e.g. glue, nails, screws, etc). If in doubt, ask me. o You must include the cost of any specialty tools required for your assembly that are not available in the machine shop (even if they are your own)

• Section 1: Design Description (<2/3 page) o Describe your design, including a SCHEMATIC, a PHOTOGRAPH, and a description of materials/items used o Describe why you chose your design • Section 2: Analysis (only as much length as is necessary to clearly communicate your analysis). Note that scanning handwritten resistance networks may be faster/easier than creating digital figures. o Estimate the rate in Watts at which sunlight is absorbed by your design (assume a solar flux of 1000 W/m2) o Show a thermal resistance network for each heat transfer path for the heat loss from your design. Calculate/estimate all thermal resistances. For all convection correlations, list the assumed geometry, the equation being used, and the calculated ‘h’ value. o Identify the dominant mode of heat loss, and discuss why this is the case. o STATE AND JUSTIFY all assumptions and estimates in the analysis. And by “justify” I mean “PROVE to me that your assumption is reasonable” • Section 3: Reflection (<1/2 page) o Suggest TWO design modifications that would significantly reduce the heat loss from your design. One modification must be a low-­‐cost modification that would fit within your project budget, and the other modification must be a modification using commercially available materials/technologies that would be realistically used in industry (i.e. without an absurd cost constraint). Note that you will have to perform some independent research on available materials and technologies to complete this. • Section 4: Bill of Materials o List ALL materials in the design (automatic 20% grade reduction for any material I find in your design that is unaccounted for in your bill of materials) o Can treat scavenged items as zero cost only if anyone could reasonably attain them freely (for donated items you must count the full purchase cost) o For structural materials, you must use the minimum UNIT COST, not a portion cost (i.e. if you buy an item in its smallest available quantity and only use 10% of the item, you still must include the TOTAL item cost) o For fastening/assembly/filler materials, you may use portion costs (e.g. glue, nails, screws, etc). If in doubt, ask me. o You must include the cost of any specialty tools required for your assembly that are not available in the machine shop (even if they are your own)

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PHSX 220 Homework 13 Paper – Due Online April 28 – 5:00 pm SHM and Wave the Equation Problem 1: A hanging mass system with a mass of 85 kg, spring constant of k= 490 N/m is realeased from rest from a distance of 10 meters below the systems equilibrium position (similar values to the bottom of a bungee jump). Calculate the following quantities in regards to this system after being released at t=0: a) The angular frequency of the system (radians/sec) b) The frequency of oscillations for the system (Hz) c) The period of oscillations for the system (seconds) d) The time it takes to get back to the equilibrium position of the system for the rst time Problem 2: A horizontal spring-mass system (mass of 2:21×10􀀀25 kg) with no friction has an ocsillation frequency of 9,192,631,770 cycles per second. (a second is de ned by 9,192,631,770 cycles of a Cs-133 atom)). Calculate the e ective spring constant of the system Problem 3: A swinging person, such as Tarzan, can be modeled after a simple pendulum with a mass of 85 kg and a length of 10 m. Consider the mass being released from rest at t=0 at an angle of +15 degrees from the vertical. Calculate the following quantities in regards to this system. You need to be in radians mode for this problem a) The angular frequency of the system (radians/sec) b) The frequency of oscillations for the system in (Hz) c) The period of oscillations of the system (seconds) d) Sketch plots of the angular position, angular velocity and angular acceleration of the system as a function of time. Hint: These will always help you with these time to it takes to a certain point in it’s cycle questions. e) The time it takes for the mass to get half way through its rst cycle (or to the other side of the swing if you were interested in timing say a rescue e ort or something along those lines) . f) The maximum angular velocity of the mass g) The maximum angular accleration of the mass h) The magnitude of the angular momentum of the mass at 3 seconds i) The magnitude of the torque acting on the mass at 3 seconds Problem 4: A wave has a wavenumber of 1 m-1, and an angular frequency of 2 radians per second, travels in the +x direction and has a maximum transverse amplitude of 0.1 m. At t=0, and x =0 the y position is equal to 0.0 m (y(0,0) = 0.0 m). a) Calculate the wavelength of the wave b) Calculate the period of oscillations for the wave c) Calculate the wave speed along the x axis d) Calculate the magnitude and direction of the transverse position of the wave at x=0.5 m and t = 8s e) Calculate the magnitude and direction of the transverse velocity of the wave at x=0.5 m and t = 8s f) Calculate the magnitude and direction of the transverse acceleration of the wave at x=0.5 m and t = 8s Problem 5-6: Chapter 16 Problem 10, 22 Additional Suggested Problems with Solutions Provided: Chapter 16 Problems 5, 9, 15, 45

PHSX 220 Homework 13 Paper – Due Online April 28 – 5:00 pm SHM and Wave the Equation Problem 1: A hanging mass system with a mass of 85 kg, spring constant of k= 490 N/m is realeased from rest from a distance of 10 meters below the systems equilibrium position (similar values to the bottom of a bungee jump). Calculate the following quantities in regards to this system after being released at t=0: a) The angular frequency of the system (radians/sec) b) The frequency of oscillations for the system (Hz) c) The period of oscillations for the system (seconds) d) The time it takes to get back to the equilibrium position of the system for the rst time Problem 2: A horizontal spring-mass system (mass of 2:21×10􀀀25 kg) with no friction has an ocsillation frequency of 9,192,631,770 cycles per second. (a second is de ned by 9,192,631,770 cycles of a Cs-133 atom)). Calculate the e ective spring constant of the system Problem 3: A swinging person, such as Tarzan, can be modeled after a simple pendulum with a mass of 85 kg and a length of 10 m. Consider the mass being released from rest at t=0 at an angle of +15 degrees from the vertical. Calculate the following quantities in regards to this system. You need to be in radians mode for this problem a) The angular frequency of the system (radians/sec) b) The frequency of oscillations for the system in (Hz) c) The period of oscillations of the system (seconds) d) Sketch plots of the angular position, angular velocity and angular acceleration of the system as a function of time. Hint: These will always help you with these time to it takes to a certain point in it’s cycle questions. e) The time it takes for the mass to get half way through its rst cycle (or to the other side of the swing if you were interested in timing say a rescue e ort or something along those lines) . f) The maximum angular velocity of the mass g) The maximum angular accleration of the mass h) The magnitude of the angular momentum of the mass at 3 seconds i) The magnitude of the torque acting on the mass at 3 seconds Problem 4: A wave has a wavenumber of 1 m-1, and an angular frequency of 2 radians per second, travels in the +x direction and has a maximum transverse amplitude of 0.1 m. At t=0, and x =0 the y position is equal to 0.0 m (y(0,0) = 0.0 m). a) Calculate the wavelength of the wave b) Calculate the period of oscillations for the wave c) Calculate the wave speed along the x axis d) Calculate the magnitude and direction of the transverse position of the wave at x=0.5 m and t = 8s e) Calculate the magnitude and direction of the transverse velocity of the wave at x=0.5 m and t = 8s f) Calculate the magnitude and direction of the transverse acceleration of the wave at x=0.5 m and t = 8s Problem 5-6: Chapter 16 Problem 10, 22 Additional Suggested Problems with Solutions Provided: Chapter 16 Problems 5, 9, 15, 45

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