Lab Description: Follow the instructions in the lab tasks below to complete Problems 3 and 4 of Project 10 from the Digilent Real Digital website. These are two design problems involving finite state machine design and interfacing with seven-segment display. First start by analyzing the block diagram for Problem 3 of Project 10. Then, use VHDL to design each of the system components. You will need to use four separate design modules and instantiate each of these within a fifth design module for the overall system. For Problem 4 of Project 10, carefully read through the problem and the “Seven-Segment Display” section of the FPGA board’s user guide before carefully planning the design of this system. Lab Tasks: 1. Complete Problem 3 of Project 10 (a single-digit stopwatch): a. Pay particular attention to the block diagram displayed for this problem. Create each of the four components to this system: i. Seven-segment decoder: You will be able to reuse your design from Lab 2 ii. 4-bit counter: I recommend taking a look at the behavior binary counter illustrated in “Binary counters in VHDL” from Module 10 iii. Clock divider: You will be able to reuse your design from Lab 5. However, you will have to revise this design for task 2. For more information, I recommend taking a look at “Binary counters in VHDL” from Module 10 for information about clock dividers. Note: The stopwatch circuit will increment the digit once every second. Design your clock divider accordingly in order to meet this timing specification. Remember, the clock on the lab FPGA board (Spartan 3) has a frequency of 50 MHz. If you purchased your board, the FPGA Basys 3 or Nexys 4 DDR FPGA board has a frequency of 100 MHz. iv. Controller: This is the main component you will design using a finite state machine b. Use VHDL test benches to verify the correct operation of your 4-bit counter, clock divider (I suggest you use a small divider value for simulating so you do not have to simulate for a long duration), controller, and overall system (again, I suggest you use a small divider value for simulating) c. Ask the instructor to check your designs, simulation waveforms, and FPGA board implementation for your circuit 2. Complete Problem 4 of Project 10 (a multi-digit stopwatch): a. Note: The least-significant digit should change at a rate of once per millisecond. However, for our design, the most-significant bit will not change once per second since each digit will count from 0-F. b. For more information about the timing and pinouts of the seven-segment display, please refer to your board’s user guide from Digilent’s website. Or use this direct link to our lab’s Spartan 3 FPGA board’s user guide. Look for a heading named “Seven-Segment Display” for more information about the timing requirements. c. Use VHDL test benches to verify the correct operation of your system and its components (again, I suggest you use a small divider value for simulating) d. Ask the instructor to check your designs, simulation waveforms, and FPGA board implementation for your circuit 3. If you complete both of the tasks above, then you may continue and complete one or both of the following extra credit tasks: a. Decimal, Multi-Digit Stopwatch (extra credit task) You may complete this extra credit task instead of the hexadecimal, multi-digit stopwatch (lab task 2), or you may complete lab task 2 first, then complete this task i. Modify/create a multi-digit stopwatch so that only decimal numbers are displayed. The least-significant digit should change at a rate of once per millisecond and the most-significant bit will change once per second. This will now act like a real stopwatch. ii. Use VHDL test benches to verify the correct operation of your system and its components (again, I suggest you use a small divider value for simulating) iii. Ask the instructor to check your designs, simulation waveforms, and FPGA board implementation for your circuit iv. Answer the extra credit lab task A questions on the cover sheet. In addition, list any references you use for this extra credit task. b. A Blinking, Multi-Digit Stopwatch (extra credit task) You may complete this extra credit task by altering your design of the hexadecimal or decimal multidigit stopwatch i. Modify your multi-digit stopwatch so the seven-segment display will blink rapidly once the most-significant digit is 9 or greater (to signal the stopwatch is close to the maximum value). This is your chance to design the system you described in the discussion question on the cover sheet. You may choose an appropriate rate at which the seven-segment display will blink. ii. Use VHDL test benches to verify the correct operation of your system and its components (again, I suggest you use a small divider value for simulating) iii. Ask the instructor to check your designs, simulation waveforms, and FPGA board implementation for your circuit iv. Answer the extra credit lab task B questions on the cover sheet. In addition, list any references you use for this extra credit task.

Lab Description: Follow the instructions in the lab tasks below to complete Problems 3 and 4 of Project 10 from the Digilent Real Digital website. These are two design problems involving finite state machine design and interfacing with seven-segment display. First start by analyzing the block diagram for Problem 3 of Project 10. Then, use VHDL to design each of the system components. You will need to use four separate design modules and instantiate each of these within a fifth design module for the overall system. For Problem 4 of Project 10, carefully read through the problem and the “Seven-Segment Display” section of the FPGA board’s user guide before carefully planning the design of this system. Lab Tasks: 1. Complete Problem 3 of Project 10 (a single-digit stopwatch): a. Pay particular attention to the block diagram displayed for this problem. Create each of the four components to this system: i. Seven-segment decoder: You will be able to reuse your design from Lab 2 ii. 4-bit counter: I recommend taking a look at the behavior binary counter illustrated in “Binary counters in VHDL” from Module 10 iii. Clock divider: You will be able to reuse your design from Lab 5. However, you will have to revise this design for task 2. For more information, I recommend taking a look at “Binary counters in VHDL” from Module 10 for information about clock dividers. Note: The stopwatch circuit will increment the digit once every second. Design your clock divider accordingly in order to meet this timing specification. Remember, the clock on the lab FPGA board (Spartan 3) has a frequency of 50 MHz. If you purchased your board, the FPGA Basys 3 or Nexys 4 DDR FPGA board has a frequency of 100 MHz. iv. Controller: This is the main component you will design using a finite state machine b. Use VHDL test benches to verify the correct operation of your 4-bit counter, clock divider (I suggest you use a small divider value for simulating so you do not have to simulate for a long duration), controller, and overall system (again, I suggest you use a small divider value for simulating) c. Ask the instructor to check your designs, simulation waveforms, and FPGA board implementation for your circuit 2. Complete Problem 4 of Project 10 (a multi-digit stopwatch): a. Note: The least-significant digit should change at a rate of once per millisecond. However, for our design, the most-significant bit will not change once per second since each digit will count from 0-F. b. For more information about the timing and pinouts of the seven-segment display, please refer to your board’s user guide from Digilent’s website. Or use this direct link to our lab’s Spartan 3 FPGA board’s user guide. Look for a heading named “Seven-Segment Display” for more information about the timing requirements. c. Use VHDL test benches to verify the correct operation of your system and its components (again, I suggest you use a small divider value for simulating) d. Ask the instructor to check your designs, simulation waveforms, and FPGA board implementation for your circuit 3. If you complete both of the tasks above, then you may continue and complete one or both of the following extra credit tasks: a. Decimal, Multi-Digit Stopwatch (extra credit task) You may complete this extra credit task instead of the hexadecimal, multi-digit stopwatch (lab task 2), or you may complete lab task 2 first, then complete this task i. Modify/create a multi-digit stopwatch so that only decimal numbers are displayed. The least-significant digit should change at a rate of once per millisecond and the most-significant bit will change once per second. This will now act like a real stopwatch. ii. Use VHDL test benches to verify the correct operation of your system and its components (again, I suggest you use a small divider value for simulating) iii. Ask the instructor to check your designs, simulation waveforms, and FPGA board implementation for your circuit iv. Answer the extra credit lab task A questions on the cover sheet. In addition, list any references you use for this extra credit task. b. A Blinking, Multi-Digit Stopwatch (extra credit task) You may complete this extra credit task by altering your design of the hexadecimal or decimal multidigit stopwatch i. Modify your multi-digit stopwatch so the seven-segment display will blink rapidly once the most-significant digit is 9 or greater (to signal the stopwatch is close to the maximum value). This is your chance to design the system you described in the discussion question on the cover sheet. You may choose an appropriate rate at which the seven-segment display will blink. ii. Use VHDL test benches to verify the correct operation of your system and its components (again, I suggest you use a small divider value for simulating) iii. Ask the instructor to check your designs, simulation waveforms, and FPGA board implementation for your circuit iv. Answer the extra credit lab task B questions on the cover sheet. In addition, list any references you use for this extra credit task.

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