Researchers recently investigated whether or not coffee prevented the development of high blood sugar (hyperglycemia) in laboratory mice. The mice used in this experiment have a mutation that makes them become diabetic. Read about this research study in this article published on the Science Daily web-site New Evidence That Drinking Coffee May Reduce the Risk of Diabetes as well as the following summary: A group of 11 mice was given water, and another group of 10 mice was supplied with diluted black coffee (coffee:water 1:1) as drinking fluids for five weeks. The composition of the diets and living conditions were similar for both groups of mice. Blood glucose was monitored weekly for all mice. After five weeks, there was no change in average body weight between groups. Results indicated that blood glucose concentrations increased significantly in the mice that drank water compared with those that were supplied with coffee. Finally, blood glucose concentration in the coffee group exhibited a 30 percent decrease compared with that in the water group. In the original paper, the investigators acknowledged that the coffee for the experiment was supplied as a gift from a corporation. Then answer the following questions in your own words: 1. Identify and describe the steps of the scientific method. Which observations do you think the scientists made leading up to this research study? Given your understanding of the experimental design, formulate a specific hypothesis that is being tested in this experiment. Describe the experimental design including control and treatment group(s), and dependent and independent variables. Summarize the results and the conclusion (50 points) 2. Criticize the research described. Things to consider: Were the test subjects and treatments relevant and appropriate? Was the sample size large enough? Were the methods used appropriate? Can you think of a potential bias in a research study like this? What are the limitations of the conclusions made in this research study? Address at least two of these questions in your critique of the research study (20 points). 3. Discuss the relevance of this type of research, both for the world in general and for you personally (20 points). 4. Write answers in your own words with proper grammar and spelling (10 points)

Researchers recently investigated whether or not coffee prevented the development of high blood sugar (hyperglycemia) in laboratory mice. The mice used in this experiment have a mutation that makes them become diabetic. Read about this research study in this article published on the Science Daily web-site New Evidence That Drinking Coffee May Reduce the Risk of Diabetes as well as the following summary: A group of 11 mice was given water, and another group of 10 mice was supplied with diluted black coffee (coffee:water 1:1) as drinking fluids for five weeks. The composition of the diets and living conditions were similar for both groups of mice. Blood glucose was monitored weekly for all mice. After five weeks, there was no change in average body weight between groups. Results indicated that blood glucose concentrations increased significantly in the mice that drank water compared with those that were supplied with coffee. Finally, blood glucose concentration in the coffee group exhibited a 30 percent decrease compared with that in the water group. In the original paper, the investigators acknowledged that the coffee for the experiment was supplied as a gift from a corporation. Then answer the following questions in your own words: 1. Identify and describe the steps of the scientific method. Which observations do you think the scientists made leading up to this research study? Given your understanding of the experimental design, formulate a specific hypothesis that is being tested in this experiment. Describe the experimental design including control and treatment group(s), and dependent and independent variables. Summarize the results and the conclusion (50 points) 2. Criticize the research described. Things to consider: Were the test subjects and treatments relevant and appropriate? Was the sample size large enough? Were the methods used appropriate? Can you think of a potential bias in a research study like this? What are the limitations of the conclusions made in this research study? Address at least two of these questions in your critique of the research study (20 points). 3. Discuss the relevance of this type of research, both for the world in general and for you personally (20 points). 4. Write answers in your own words with proper grammar and spelling (10 points)

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3. The probability density function for mechanical component is given by: fT(t) = 1/(b-a) when t <=a<=b = 0; elsewhere Determine: • Cumulative distribution of the failures (5 points) • Reliability of the components (5 points) • Hazard rate for the components (5 points) • Mean, standard deviation of the failure distribution and reliability of components at the end of 2 years, when c=0.0025 (5 points) • Plot the probability density function, probability time distribution function, Reliability function and Hard Rate function for the given distribution when a=6000 and b=12000 (5 points)

3. The probability density function for mechanical component is given by: fT(t) = 1/(b-a) when t <=a<=b = 0; elsewhere Determine: • Cumulative distribution of the failures (5 points) • Reliability of the components (5 points) • Hazard rate for the components (5 points) • Mean, standard deviation of the failure distribution and reliability of components at the end of 2 years, when c=0.0025 (5 points) • Plot the probability density function, probability time distribution function, Reliability function and Hard Rate function for the given distribution when a=6000 and b=12000 (5 points)

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Chapter 4 Practice Problems (Practice – no credit) Due: 11:59pm on Friday, February 14, 2014 You will receive no credit for items you complete after the assignment is due. Grading Policy Advice for the Quarterback A quarterback is set up to throw the football to a receiver who is running with a constant velocity directly away from the quarterback and is now a distance away from the quarterback. The quarterback figures that the ball must be thrown at an angle to the horizontal and he estimates that the receiver must catch the ball a time interval after it is thrown to avoid having opposition players prevent the receiver from making the catch. In the following you may assume that the ball is thrown and caught at the same height above the level playing field. Assume that the y coordinate of the ball at the instant it is thrown or caught is and that the horizontal position of the quaterback is . Use for the magnitude of the acceleration due to gravity, and use the pictured inertial coordinate system when solving the problem. Part A Find , the vertical component of the velocity of the ball when the quarterback releases it. Express in terms of and . Hint 1. Equation of motion in y direction What is the expression for , the height of the ball as a function of time? Answer in terms of , , and . v r D  tc y = 0 x = 0 g v0y v0y tc g y(t) t g v0y

Chapter 4 Practice Problems (Practice – no credit) Due: 11:59pm on Friday, February 14, 2014 You will receive no credit for items you complete after the assignment is due. Grading Policy Advice for the Quarterback A quarterback is set up to throw the football to a receiver who is running with a constant velocity directly away from the quarterback and is now a distance away from the quarterback. The quarterback figures that the ball must be thrown at an angle to the horizontal and he estimates that the receiver must catch the ball a time interval after it is thrown to avoid having opposition players prevent the receiver from making the catch. In the following you may assume that the ball is thrown and caught at the same height above the level playing field. Assume that the y coordinate of the ball at the instant it is thrown or caught is and that the horizontal position of the quaterback is . Use for the magnitude of the acceleration due to gravity, and use the pictured inertial coordinate system when solving the problem. Part A Find , the vertical component of the velocity of the ball when the quarterback releases it. Express in terms of and . Hint 1. Equation of motion in y direction What is the expression for , the height of the ball as a function of time? Answer in terms of , , and . v r D  tc y = 0 x = 0 g v0y v0y tc g y(t) t g v0y

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Lab Description: Follow the instructions in the lab tasks below to behaviorially create and simulate a flip-flop. Afterwards, you will create a register and Arithmetic Logic Unit (ALU). Refer to Module 7 from the Digilent Real Digital website for more information about ALUs. These two components are the main components required to create an accumulator datapath. This accumulator datapath will act like a simple processor; the ALU will execute simple arithmetic/logic operations and each result will be stored in the register. In an accumulator, the value of the register will be upedated with each operation; the register is used as an input to the ALU and the newly computed result of the operation will be stored back into the register. You will create and implement this accumulator datapath in the last task of this lab. However, you will need to add an additional component to enable it to clearly operate on the FPGA board. You will create and use a clock divider to create a slower version of the FPGA board’s clock when you implement the accumulator datapath on the FPGA board. Refer to Module 10 from the Digilent Real Digital website for more information about clock dividers. Lab Tasks: 1. Create a behavioral VHDL module for a Rising-Edge Triggered (RET) D-Flip-Flop (DFF): a. In your design, use inputs “D” (data), “CLK” (the clock), “RST” (an asynchronous reset), “SET” (a synchronous set or preset signal), “CE” (clock enable), and output “Q” b. Create a VHDL test bench and simulate the flip-flop. Be sure to show the following behaviors with your simulation: i. The output “Q” sampling a ‘0’ from the input “D” ii. The output “Q” sampling a ‘1’ from the input “D” iii. The correct operation of the asynchronous reset iv. The correct operation of the synchronous preset v. The correct operation of the clock enable c. Include a screenshot of your simulation on the lab’s cover sheet. Label each of these behaviors on the waveform (it is ok to print out your cover sheet and write each behavior on the waveform). 2. Create a behavioral VHDL module for a 4-bit Arithmetic Logic Unit (ALU): a. I suggest you refer to Module 7 from the Digilent Real Digital website (in particular, the sections about ALU circuits and behavioral VHDL ALU descriptions). This 4-bit ALU will calculate arithmetic and logical expressions on two 4-bit numbers. Use behavioral expressions for the arithmetic and logic expressions (do not use port map statements to create a structural design using your ripple-carry adder from lab 3). Assume that the select input (or opcode) is 2-bits and is defined as shown in the table below: Opcode Function 00 A 01 A plus 1 10 A plus B 11 A and B b. Create a VHDL test bench to test your ALU. Use two input signal (the 4-bit values for A and B) combinations to test each operation of the ALU. Simulate your design and verify your output. Include a screenshot of your simulation on the lab’s cover sheet. 3. Create an accumulator datapath: a. First, create a 4-bit register. This is very similar to your flip-flop design from lab task 1. Ensure that your 4-bit register has inputs “D” (data), “CLK” (the clock), and “RST” (an asynchronous reset), and an output “Q”. Create a test bench and ensure that your 4-bit register operates correctly. b. Next, create a design module for the accumulator datapath and import your 4-bit register, 4-bit ALU, and seven-sgement display decoder (from lab 2) as components to this system. Connect your register, ALU, and seven-segment display decoder as follows: i. Connect the output of your ALU to the “D” input of your register ii. Connect the “Q” output of your register to both the “A” input of your ALU and the input of your seven-segement display iii. You should be left with four overall inputs: the “B” input of your ALU, the opcode input of your ALU, the CLK, and RST iv. You should be left with one overall output: the seven-segment display output c. Create a test bench to simulate the behavior of your accumulator datapath. In your test bench, simulate a few clock cycles to verify the correct operation of your system. d. Before implementing this system on the FPGA board, create and add one additional component to your system. Create and add a clock divider to this system; the input will be the board’s clock and the output will be a slower version of the clock to use for the register. Design your clock divider to slow the clock frequency to 1 Hz (1 clock cycle per second). Note that the clock on the lab FPGA board (Spartan 3) has a frequency of 50 MHz. If you purchased your board, the FPGA Basys 3 or Nexys 4 DDR FPGA board has a frequency of 100 MHz. I highly recommend taking a look at “Binary counters in VHDL” from Module 10 from the Digilent Real Digital website for information about clock dividers. e. Now, implement this system on the FPGA board. Connect the data input to four switches, connect the ALU opcode inputs to two buttons, the RST signal to one button, the CLK signal to the board’s clock, and the seven-segment display output to the seven-segment display. f. Ask the instructor to check your design, simulation waveforms, and FPGA board implementation of your circuit

Lab Description: Follow the instructions in the lab tasks below to behaviorially create and simulate a flip-flop. Afterwards, you will create a register and Arithmetic Logic Unit (ALU). Refer to Module 7 from the Digilent Real Digital website for more information about ALUs. These two components are the main components required to create an accumulator datapath. This accumulator datapath will act like a simple processor; the ALU will execute simple arithmetic/logic operations and each result will be stored in the register. In an accumulator, the value of the register will be upedated with each operation; the register is used as an input to the ALU and the newly computed result of the operation will be stored back into the register. You will create and implement this accumulator datapath in the last task of this lab. However, you will need to add an additional component to enable it to clearly operate on the FPGA board. You will create and use a clock divider to create a slower version of the FPGA board’s clock when you implement the accumulator datapath on the FPGA board. Refer to Module 10 from the Digilent Real Digital website for more information about clock dividers. Lab Tasks: 1. Create a behavioral VHDL module for a Rising-Edge Triggered (RET) D-Flip-Flop (DFF): a. In your design, use inputs “D” (data), “CLK” (the clock), “RST” (an asynchronous reset), “SET” (a synchronous set or preset signal), “CE” (clock enable), and output “Q” b. Create a VHDL test bench and simulate the flip-flop. Be sure to show the following behaviors with your simulation: i. The output “Q” sampling a ‘0’ from the input “D” ii. The output “Q” sampling a ‘1’ from the input “D” iii. The correct operation of the asynchronous reset iv. The correct operation of the synchronous preset v. The correct operation of the clock enable c. Include a screenshot of your simulation on the lab’s cover sheet. Label each of these behaviors on the waveform (it is ok to print out your cover sheet and write each behavior on the waveform). 2. Create a behavioral VHDL module for a 4-bit Arithmetic Logic Unit (ALU): a. I suggest you refer to Module 7 from the Digilent Real Digital website (in particular, the sections about ALU circuits and behavioral VHDL ALU descriptions). This 4-bit ALU will calculate arithmetic and logical expressions on two 4-bit numbers. Use behavioral expressions for the arithmetic and logic expressions (do not use port map statements to create a structural design using your ripple-carry adder from lab 3). Assume that the select input (or opcode) is 2-bits and is defined as shown in the table below: Opcode Function 00 A 01 A plus 1 10 A plus B 11 A and B b. Create a VHDL test bench to test your ALU. Use two input signal (the 4-bit values for A and B) combinations to test each operation of the ALU. Simulate your design and verify your output. Include a screenshot of your simulation on the lab’s cover sheet. 3. Create an accumulator datapath: a. First, create a 4-bit register. This is very similar to your flip-flop design from lab task 1. Ensure that your 4-bit register has inputs “D” (data), “CLK” (the clock), and “RST” (an asynchronous reset), and an output “Q”. Create a test bench and ensure that your 4-bit register operates correctly. b. Next, create a design module for the accumulator datapath and import your 4-bit register, 4-bit ALU, and seven-sgement display decoder (from lab 2) as components to this system. Connect your register, ALU, and seven-segment display decoder as follows: i. Connect the output of your ALU to the “D” input of your register ii. Connect the “Q” output of your register to both the “A” input of your ALU and the input of your seven-segement display iii. You should be left with four overall inputs: the “B” input of your ALU, the opcode input of your ALU, the CLK, and RST iv. You should be left with one overall output: the seven-segment display output c. Create a test bench to simulate the behavior of your accumulator datapath. In your test bench, simulate a few clock cycles to verify the correct operation of your system. d. Before implementing this system on the FPGA board, create and add one additional component to your system. Create and add a clock divider to this system; the input will be the board’s clock and the output will be a slower version of the clock to use for the register. Design your clock divider to slow the clock frequency to 1 Hz (1 clock cycle per second). Note that the clock on the lab FPGA board (Spartan 3) has a frequency of 50 MHz. If you purchased your board, the FPGA Basys 3 or Nexys 4 DDR FPGA board has a frequency of 100 MHz. I highly recommend taking a look at “Binary counters in VHDL” from Module 10 from the Digilent Real Digital website for information about clock dividers. e. Now, implement this system on the FPGA board. Connect the data input to four switches, connect the ALU opcode inputs to two buttons, the RST signal to one button, the CLK signal to the board’s clock, and the seven-segment display output to the seven-segment display. f. Ask the instructor to check your design, simulation waveforms, and FPGA board implementation of your circuit

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1. Develop a thought experiment that attempts to uncover hidden assumptions about human freedom. 2. Find a paragraph from a book, magazine, ect. First, tell whether there are claims in the paragraph. If there are, identify the types of claims (descriptive, normative, a priori, a posteriori) in the paragraph

1. Develop a thought experiment that attempts to uncover hidden assumptions about human freedom. 2. Find a paragraph from a book, magazine, ect. First, tell whether there are claims in the paragraph. If there are, identify the types of claims (descriptive, normative, a priori, a posteriori) in the paragraph

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Q1: A small town has two banks A and B. It is estimated that 45% of the potential customers do business only with bank A, 30% only with bank B, and 15% with both banks A and B. The remaining 10% of the customers do business with none of the banks. If E1(E2) denotes the event of a randomly selected customer doing business with bank A(B), find the following probabilities: P(E1), P(E2), P(E1∩E2),P(Ē1Ē2) and P(Ē1UE2) Q2: The inspection of a batch of laminated composite beams produced in a company for defects yielded the following data: No. of defects Proportion of Beams with defects inside Proportion of Beams with defects on surface Total 0 0.4 0.15 0.55 1 0.1 0.05 0.15 2 0.07 0.03 0.1 3 0.06 0.02 0.08 4 0.02 0.03 0.05 5 or more 0.03 0.04 0.07 Total 0.68 0.32 1.0 Determine the probability that the beam has a defect on the surface or it has 4 or more defects. Q3. A batch of 1000 piston rings manufactured in an engine manufacturing facility contains 40% defective. Two piston rings are randomly selected from the batch, one at a time, without replacement. If Ei denotes the event that the i th piston ring selected is defective (i=1, 2), determine the values, P(E1) and P(E2). Q4. An automobile transmission can fail due to three types of problems i.e. gear failure, bearing failure, or shaft failure, wit probabilities 0.3, 0.5 an 0.2 respectively. The probability of transmission failure given a gear failure is 0.5, given a bearing failure is 0.5 and given a shaft failure is 0.6. If a transmission fails, what is the most likely cause? Q5. In the manufacture of a fiber-reinforced laminated composite material, the following probabilities can be associated with the failure of the components made out of this material: Prob. Of failure of components Level of defect in material 0.2 High 0.05 Medium 0.01 Low In a batch of composite material manufactured, 10% of material is found to have High defects, 30% to Medium level defects and 60% to Low level of defects. For a component using this batch of material, indicate the various events associated with the failure of component as a Tree diagram. Also, determine the probability that the component fails.

Q1: A small town has two banks A and B. It is estimated that 45% of the potential customers do business only with bank A, 30% only with bank B, and 15% with both banks A and B. The remaining 10% of the customers do business with none of the banks. If E1(E2) denotes the event of a randomly selected customer doing business with bank A(B), find the following probabilities: P(E1), P(E2), P(E1∩E2),P(Ē1Ē2) and P(Ē1UE2) Q2: The inspection of a batch of laminated composite beams produced in a company for defects yielded the following data: No. of defects Proportion of Beams with defects inside Proportion of Beams with defects on surface Total 0 0.4 0.15 0.55 1 0.1 0.05 0.15 2 0.07 0.03 0.1 3 0.06 0.02 0.08 4 0.02 0.03 0.05 5 or more 0.03 0.04 0.07 Total 0.68 0.32 1.0 Determine the probability that the beam has a defect on the surface or it has 4 or more defects. Q3. A batch of 1000 piston rings manufactured in an engine manufacturing facility contains 40% defective. Two piston rings are randomly selected from the batch, one at a time, without replacement. If Ei denotes the event that the i th piston ring selected is defective (i=1, 2), determine the values, P(E1) and P(E2). Q4. An automobile transmission can fail due to three types of problems i.e. gear failure, bearing failure, or shaft failure, wit probabilities 0.3, 0.5 an 0.2 respectively. The probability of transmission failure given a gear failure is 0.5, given a bearing failure is 0.5 and given a shaft failure is 0.6. If a transmission fails, what is the most likely cause? Q5. In the manufacture of a fiber-reinforced laminated composite material, the following probabilities can be associated with the failure of the components made out of this material: Prob. Of failure of components Level of defect in material 0.2 High 0.05 Medium 0.01 Low In a batch of composite material manufactured, 10% of material is found to have High defects, 30% to Medium level defects and 60% to Low level of defects. For a component using this batch of material, indicate the various events associated with the failure of component as a Tree diagram. Also, determine the probability that the component fails.

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ENGR 2010 (Section 02) – Assignment 7 Due: Wednesday November 25th, 11:59 pm Points: 20 Prof. Lei Reading: Sections 6.2-6.3 of Nilsson and Riedel, Electric Circuits, 9th Edition Submit electronic solutions (i.e. using Microsoft Word or a scanned copy of your written work) to the following problems on Blackboard. To receive credit, you must show work indicating how you arrived at each final answer. Problem 1 Consider the RC circuit on the right. and suppose that Vs(t) is a time-varying voltage input shown at the bottom. a) Suppose VC(0) = 0V. Plot VR(t) and VC(t) from 0ms to 300ms. Show your work in obtaining VR(t) and VC(t). b) Suppose the capacitance value is changed to 2μF, and VC(0) = 0V. Plot VR(t) and VC(t) from 0ms to 300ms. Show your work in obtaining VR(t) and VC(t). c) Explain how VC(t) qualitatively compares with Vs(t), and how VR(t) qualitatively compares with Vs(t). d) Explain how the capacitance value affects VC(t). t Vs(t) 1V -1V 50ms 100ms 150ms 200ms 250ms + – Vs(t) 100000 Ohms 1 uF + – VC(t) + – VR(t) 0ms 300ms Note: Capacitors are often used to protect against sudden changes in a voltage value, which could damage electronic components. Here, Vs(t) undergoes many sudden changes, but VC(t) undergoes less change. Problem 2 Using PSpice, perform two transient analysis simulations – one for the circuit in part (a), and one for the circuit in part(b) of problem 1 – to verify that your plots in problem 1 are correct. For each simulation, plot the traces for VR(t) and VC(t). Hint: You may need to perform arithmetic operations between simulation traces. Take a screenshot of your constructed circuits and the simulation traces for VR(t) and VC(t), which you will submit onto Blackboard. t Vs(t) 1V -1V 50ms 100ms 150ms 200ms 250ms + – Vs(t) 100000 Ohms 1 uF + – VC(t) + – VR(t) 0ms 300ms 1 uF or 2 uF Problem 3 Consider the Resistor-Diode circuit on the right, and suppose that Vs(t) is a time-varying voltage input shown at the bottom. Suppose that for the diode to turn on, it needs 0.7V between the positive and negative terminals. a) Plot VR(t) and VD(t) from 0ms to 300ms b) Explain how VD(t) qualitatively compares with Vs(t), and how VR(t) qualitatively compares with Vs(t). t Vs(t) 1V -1V 50ms 100ms 0ms 150ms 200ms 250ms 300ms + – Vs(t) 100000 Ohms + – VD(t) + – VR(t) Problem 4 Using PSpice, perform a transient analysis simulation for the circuit in problem 3 – to verify that your plots in problem 3 are correct. For the simulation, plot the traces for VR(t) and VD(t). To create the diode in PSpice, use the Dbreak component. After placing the component on the page, highlight the component, and edit the Pspice model (Edit -> PSpice Model) and set Rs to 0. Hint: You may need to perform arithmetic operations between simulation traces. Take a screenshot of your constructed circuit and the simulation traces for VR(t) and VD(t), which you will submit onto Blackboard. Note that your simulation trace plots may not be exactly the same as those from Problem 3, since the PSpice diode model has a turn-on voltage that’s not exactly 0.7V. t Vs(t) 1V -1V 50ms 100ms 0ms 150ms 200ms 250ms 300ms + – Vs(t) 100000 Ohms + – VD(t) + – VR(t) Problem 5 (Bonus: 5 points) In the circuit from problem 1 (shown on the right), write several sentences to explain why VC(t) is often referred to as the “low-pass filtered” output, and VR(t) is often referred to as the “high-pass filtered” output. You will need to look up the definitions for “low-pass” and “high-pass” filters. Examining your plots for VC(t) and VR(t) will help. t Vs(t) 1V -1V 50ms 100ms 150ms 200ms 250ms + – Vs(t) 100000 Ohms 1 uF + – VC(t) + – VR(t) 0ms 300ms

ENGR 2010 (Section 02) – Assignment 7 Due: Wednesday November 25th, 11:59 pm Points: 20 Prof. Lei Reading: Sections 6.2-6.3 of Nilsson and Riedel, Electric Circuits, 9th Edition Submit electronic solutions (i.e. using Microsoft Word or a scanned copy of your written work) to the following problems on Blackboard. To receive credit, you must show work indicating how you arrived at each final answer. Problem 1 Consider the RC circuit on the right. and suppose that Vs(t) is a time-varying voltage input shown at the bottom. a) Suppose VC(0) = 0V. Plot VR(t) and VC(t) from 0ms to 300ms. Show your work in obtaining VR(t) and VC(t). b) Suppose the capacitance value is changed to 2μF, and VC(0) = 0V. Plot VR(t) and VC(t) from 0ms to 300ms. Show your work in obtaining VR(t) and VC(t). c) Explain how VC(t) qualitatively compares with Vs(t), and how VR(t) qualitatively compares with Vs(t). d) Explain how the capacitance value affects VC(t). t Vs(t) 1V -1V 50ms 100ms 150ms 200ms 250ms + – Vs(t) 100000 Ohms 1 uF + – VC(t) + – VR(t) 0ms 300ms Note: Capacitors are often used to protect against sudden changes in a voltage value, which could damage electronic components. Here, Vs(t) undergoes many sudden changes, but VC(t) undergoes less change. Problem 2 Using PSpice, perform two transient analysis simulations – one for the circuit in part (a), and one for the circuit in part(b) of problem 1 – to verify that your plots in problem 1 are correct. For each simulation, plot the traces for VR(t) and VC(t). Hint: You may need to perform arithmetic operations between simulation traces. Take a screenshot of your constructed circuits and the simulation traces for VR(t) and VC(t), which you will submit onto Blackboard. t Vs(t) 1V -1V 50ms 100ms 150ms 200ms 250ms + – Vs(t) 100000 Ohms 1 uF + – VC(t) + – VR(t) 0ms 300ms 1 uF or 2 uF Problem 3 Consider the Resistor-Diode circuit on the right, and suppose that Vs(t) is a time-varying voltage input shown at the bottom. Suppose that for the diode to turn on, it needs 0.7V between the positive and negative terminals. a) Plot VR(t) and VD(t) from 0ms to 300ms b) Explain how VD(t) qualitatively compares with Vs(t), and how VR(t) qualitatively compares with Vs(t). t Vs(t) 1V -1V 50ms 100ms 0ms 150ms 200ms 250ms 300ms + – Vs(t) 100000 Ohms + – VD(t) + – VR(t) Problem 4 Using PSpice, perform a transient analysis simulation for the circuit in problem 3 – to verify that your plots in problem 3 are correct. For the simulation, plot the traces for VR(t) and VD(t). To create the diode in PSpice, use the Dbreak component. After placing the component on the page, highlight the component, and edit the Pspice model (Edit -> PSpice Model) and set Rs to 0. Hint: You may need to perform arithmetic operations between simulation traces. Take a screenshot of your constructed circuit and the simulation traces for VR(t) and VD(t), which you will submit onto Blackboard. Note that your simulation trace plots may not be exactly the same as those from Problem 3, since the PSpice diode model has a turn-on voltage that’s not exactly 0.7V. t Vs(t) 1V -1V 50ms 100ms 0ms 150ms 200ms 250ms 300ms + – Vs(t) 100000 Ohms + – VD(t) + – VR(t) Problem 5 (Bonus: 5 points) In the circuit from problem 1 (shown on the right), write several sentences to explain why VC(t) is often referred to as the “low-pass filtered” output, and VR(t) is often referred to as the “high-pass filtered” output. You will need to look up the definitions for “low-pass” and “high-pass” filters. Examining your plots for VC(t) and VR(t) will help. t Vs(t) 1V -1V 50ms 100ms 150ms 200ms 250ms + – Vs(t) 100000 Ohms 1 uF + – VC(t) + – VR(t) 0ms 300ms

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Chapter 3 Practice Problems (Practice – no credit) Due: 11:59pm on Wednesday, February 12, 2014 You will receive no credit for items you complete after the assignment is due. Grading Policy Tactics Box 3.1 Determining the Components of a Vector Learning Goal: To practice Tactics Box 3.1 Determining the Components of a Vector. When a vector is decomposed into component vectors and parallel to the coordinate axes, we can describe each component vector with a single number (a scalar) called the component. This tactics box describes how to determine the x component and y component of vector , denoted and . TACTICS BOX 3.1 Determining the components of a vector The absolute value of the x component is the magnitude of the 1. component vector . 2. The sign of is positive if points in the positive x direction; it is negative if points in the negative x direction. 3. The y component is determined similarly. Part A What is the magnitude of the component vector shown in the figure? Express your answer in meters to one significant figure. A A x A y A Ax Ay |Ax| Ax A x Ax A x A x Ay A x

Chapter 3 Practice Problems (Practice – no credit) Due: 11:59pm on Wednesday, February 12, 2014 You will receive no credit for items you complete after the assignment is due. Grading Policy Tactics Box 3.1 Determining the Components of a Vector Learning Goal: To practice Tactics Box 3.1 Determining the Components of a Vector. When a vector is decomposed into component vectors and parallel to the coordinate axes, we can describe each component vector with a single number (a scalar) called the component. This tactics box describes how to determine the x component and y component of vector , denoted and . TACTICS BOX 3.1 Determining the components of a vector The absolute value of the x component is the magnitude of the 1. component vector . 2. The sign of is positive if points in the positive x direction; it is negative if points in the negative x direction. 3. The y component is determined similarly. Part A What is the magnitude of the component vector shown in the figure? Express your answer in meters to one significant figure. A A x A y A Ax Ay |Ax| Ax A x Ax A x A x Ay A x

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Lab Description: Follow the instructions in the lab tasks below to complete Problems 3 and 4 of Project 10 from the Digilent Real Digital website. These are two design problems involving finite state machine design and interfacing with seven-segment display. First start by analyzing the block diagram for Problem 3 of Project 10. Then, use VHDL to design each of the system components. You will need to use four separate design modules and instantiate each of these within a fifth design module for the overall system. For Problem 4 of Project 10, carefully read through the problem and the “Seven-Segment Display” section of the FPGA board’s user guide before carefully planning the design of this system. Lab Tasks: 1. Complete Problem 3 of Project 10 (a single-digit stopwatch): a. Pay particular attention to the block diagram displayed for this problem. Create each of the four components to this system: i. Seven-segment decoder: You will be able to reuse your design from Lab 2 ii. 4-bit counter: I recommend taking a look at the behavior binary counter illustrated in “Binary counters in VHDL” from Module 10 iii. Clock divider: You will be able to reuse your design from Lab 5. However, you will have to revise this design for task 2. For more information, I recommend taking a look at “Binary counters in VHDL” from Module 10 for information about clock dividers. Note: The stopwatch circuit will increment the digit once every second. Design your clock divider accordingly in order to meet this timing specification. Remember, the clock on the lab FPGA board (Spartan 3) has a frequency of 50 MHz. If you purchased your board, the FPGA Basys 3 or Nexys 4 DDR FPGA board has a frequency of 100 MHz. iv. Controller: This is the main component you will design using a finite state machine b. Use VHDL test benches to verify the correct operation of your 4-bit counter, clock divider (I suggest you use a small divider value for simulating so you do not have to simulate for a long duration), controller, and overall system (again, I suggest you use a small divider value for simulating) c. Ask the instructor to check your designs, simulation waveforms, and FPGA board implementation for your circuit 2. Complete Problem 4 of Project 10 (a multi-digit stopwatch): a. Note: The least-significant digit should change at a rate of once per millisecond. However, for our design, the most-significant bit will not change once per second since each digit will count from 0-F. b. For more information about the timing and pinouts of the seven-segment display, please refer to your board’s user guide from Digilent’s website. Or use this direct link to our lab’s Spartan 3 FPGA board’s user guide. Look for a heading named “Seven-Segment Display” for more information about the timing requirements. c. Use VHDL test benches to verify the correct operation of your system and its components (again, I suggest you use a small divider value for simulating) d. Ask the instructor to check your designs, simulation waveforms, and FPGA board implementation for your circuit 3. If you complete both of the tasks above, then you may continue and complete one or both of the following extra credit tasks: a. Decimal, Multi-Digit Stopwatch (extra credit task) You may complete this extra credit task instead of the hexadecimal, multi-digit stopwatch (lab task 2), or you may complete lab task 2 first, then complete this task i. Modify/create a multi-digit stopwatch so that only decimal numbers are displayed. The least-significant digit should change at a rate of once per millisecond and the most-significant bit will change once per second. This will now act like a real stopwatch. ii. Use VHDL test benches to verify the correct operation of your system and its components (again, I suggest you use a small divider value for simulating) iii. Ask the instructor to check your designs, simulation waveforms, and FPGA board implementation for your circuit iv. Answer the extra credit lab task A questions on the cover sheet. In addition, list any references you use for this extra credit task. b. A Blinking, Multi-Digit Stopwatch (extra credit task) You may complete this extra credit task by altering your design of the hexadecimal or decimal multidigit stopwatch i. Modify your multi-digit stopwatch so the seven-segment display will blink rapidly once the most-significant digit is 9 or greater (to signal the stopwatch is close to the maximum value). This is your chance to design the system you described in the discussion question on the cover sheet. You may choose an appropriate rate at which the seven-segment display will blink. ii. Use VHDL test benches to verify the correct operation of your system and its components (again, I suggest you use a small divider value for simulating) iii. Ask the instructor to check your designs, simulation waveforms, and FPGA board implementation for your circuit iv. Answer the extra credit lab task B questions on the cover sheet. In addition, list any references you use for this extra credit task.

Lab Description: Follow the instructions in the lab tasks below to complete Problems 3 and 4 of Project 10 from the Digilent Real Digital website. These are two design problems involving finite state machine design and interfacing with seven-segment display. First start by analyzing the block diagram for Problem 3 of Project 10. Then, use VHDL to design each of the system components. You will need to use four separate design modules and instantiate each of these within a fifth design module for the overall system. For Problem 4 of Project 10, carefully read through the problem and the “Seven-Segment Display” section of the FPGA board’s user guide before carefully planning the design of this system. Lab Tasks: 1. Complete Problem 3 of Project 10 (a single-digit stopwatch): a. Pay particular attention to the block diagram displayed for this problem. Create each of the four components to this system: i. Seven-segment decoder: You will be able to reuse your design from Lab 2 ii. 4-bit counter: I recommend taking a look at the behavior binary counter illustrated in “Binary counters in VHDL” from Module 10 iii. Clock divider: You will be able to reuse your design from Lab 5. However, you will have to revise this design for task 2. For more information, I recommend taking a look at “Binary counters in VHDL” from Module 10 for information about clock dividers. Note: The stopwatch circuit will increment the digit once every second. Design your clock divider accordingly in order to meet this timing specification. Remember, the clock on the lab FPGA board (Spartan 3) has a frequency of 50 MHz. If you purchased your board, the FPGA Basys 3 or Nexys 4 DDR FPGA board has a frequency of 100 MHz. iv. Controller: This is the main component you will design using a finite state machine b. Use VHDL test benches to verify the correct operation of your 4-bit counter, clock divider (I suggest you use a small divider value for simulating so you do not have to simulate for a long duration), controller, and overall system (again, I suggest you use a small divider value for simulating) c. Ask the instructor to check your designs, simulation waveforms, and FPGA board implementation for your circuit 2. Complete Problem 4 of Project 10 (a multi-digit stopwatch): a. Note: The least-significant digit should change at a rate of once per millisecond. However, for our design, the most-significant bit will not change once per second since each digit will count from 0-F. b. For more information about the timing and pinouts of the seven-segment display, please refer to your board’s user guide from Digilent’s website. Or use this direct link to our lab’s Spartan 3 FPGA board’s user guide. Look for a heading named “Seven-Segment Display” for more information about the timing requirements. c. Use VHDL test benches to verify the correct operation of your system and its components (again, I suggest you use a small divider value for simulating) d. Ask the instructor to check your designs, simulation waveforms, and FPGA board implementation for your circuit 3. If you complete both of the tasks above, then you may continue and complete one or both of the following extra credit tasks: a. Decimal, Multi-Digit Stopwatch (extra credit task) You may complete this extra credit task instead of the hexadecimal, multi-digit stopwatch (lab task 2), or you may complete lab task 2 first, then complete this task i. Modify/create a multi-digit stopwatch so that only decimal numbers are displayed. The least-significant digit should change at a rate of once per millisecond and the most-significant bit will change once per second. This will now act like a real stopwatch. ii. Use VHDL test benches to verify the correct operation of your system and its components (again, I suggest you use a small divider value for simulating) iii. Ask the instructor to check your designs, simulation waveforms, and FPGA board implementation for your circuit iv. Answer the extra credit lab task A questions on the cover sheet. In addition, list any references you use for this extra credit task. b. A Blinking, Multi-Digit Stopwatch (extra credit task) You may complete this extra credit task by altering your design of the hexadecimal or decimal multidigit stopwatch i. Modify your multi-digit stopwatch so the seven-segment display will blink rapidly once the most-significant digit is 9 or greater (to signal the stopwatch is close to the maximum value). This is your chance to design the system you described in the discussion question on the cover sheet. You may choose an appropriate rate at which the seven-segment display will blink. ii. Use VHDL test benches to verify the correct operation of your system and its components (again, I suggest you use a small divider value for simulating) iii. Ask the instructor to check your designs, simulation waveforms, and FPGA board implementation for your circuit iv. Answer the extra credit lab task B questions on the cover sheet. In addition, list any references you use for this extra credit task.

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