Sex, Gender, and Popular Culture Spring 2015 Look through popular magazines, and see if you can find advertisements that objectify women in order to sell a product. Alternately, you may use an advertisement on television (but make sure to provide a link to the ad so I can see it!). Study these images then write a paper about objectification that deals with all or some of the following: • What effect(s), if any, do you think the objectification of women’s bodies has on our culture? • Jean Kilbourne states “turning a human being into a thing is almost always the first step toward justifying violence against that person.” What do you think she means by this? Do you agree with her reasoning? Why or why not? • Some people would argue that depicting a woman’s body as an object is a form of art. What is your opinion of this point of view? Explain your reasoning. • Why do you think that women are objectified more often than men are? • How does sexualization and objectification play out differently across racial lines? • Kilbourne explains that the consequences of being objectified are different – and more serious – for women than for men. Do you agree? How is the world different for women than it is for men? How do objectified images of women interact with those in our culture differently from the way images of men do? Why is it important to look at images in the context of the culture? • What is the difference between sexual objectification and sexual subjectification? (Ros Gill ) • How do ads construct violent white masculinity and how does that vision of masculinity hurt both men and women? Throughout your written analysis, be sure to make clear and specific reference to the images you selected, and please submit these images with your paper. Make sure you engage with and reference to at least 4 of the following authors: Kilbourne, Bordo, Hunter & Soto, Rose, Durham, Gill, Katz, Schuchardt, Ono and Buescher. Guidelines:  Keep your content focused on structural, systemic, institutional factors rather than the individual: BE ANALYTICAL NOT ANECDOTAL.  Avoid using the first person or including personal stories/reactions. You must make sure to actively engage with your readings: these essays need to be informed and framed by the theoretical material you have been reading this semester.  Keep within the 4-6 page limit; use 12-point font, double spacing and 1-inch margins.  Use formal writing conventions (introduction/thesis statement, body, conclusion) and correct grammar. Resources may be cited within the text of your paper, i.e. (Walters, 2013).

Sex, Gender, and Popular Culture Spring 2015 Look through popular magazines, and see if you can find advertisements that objectify women in order to sell a product. Alternately, you may use an advertisement on television (but make sure to provide a link to the ad so I can see it!). Study these images then write a paper about objectification that deals with all or some of the following: • What effect(s), if any, do you think the objectification of women’s bodies has on our culture? • Jean Kilbourne states “turning a human being into a thing is almost always the first step toward justifying violence against that person.” What do you think she means by this? Do you agree with her reasoning? Why or why not? • Some people would argue that depicting a woman’s body as an object is a form of art. What is your opinion of this point of view? Explain your reasoning. • Why do you think that women are objectified more often than men are? • How does sexualization and objectification play out differently across racial lines? • Kilbourne explains that the consequences of being objectified are different – and more serious – for women than for men. Do you agree? How is the world different for women than it is for men? How do objectified images of women interact with those in our culture differently from the way images of men do? Why is it important to look at images in the context of the culture? • What is the difference between sexual objectification and sexual subjectification? (Ros Gill ) • How do ads construct violent white masculinity and how does that vision of masculinity hurt both men and women? Throughout your written analysis, be sure to make clear and specific reference to the images you selected, and please submit these images with your paper. Make sure you engage with and reference to at least 4 of the following authors: Kilbourne, Bordo, Hunter & Soto, Rose, Durham, Gill, Katz, Schuchardt, Ono and Buescher. Guidelines:  Keep your content focused on structural, systemic, institutional factors rather than the individual: BE ANALYTICAL NOT ANECDOTAL.  Avoid using the first person or including personal stories/reactions. You must make sure to actively engage with your readings: these essays need to be informed and framed by the theoretical material you have been reading this semester.  Keep within the 4-6 page limit; use 12-point font, double spacing and 1-inch margins.  Use formal writing conventions (introduction/thesis statement, body, conclusion) and correct grammar. Resources may be cited within the text of your paper, i.e. (Walters, 2013).

The objectification of women has been a very controversial topic … Read More...
1 IN2009: Language Processors Coursework Part 3: The Interpreter Introduction This is the 3rd and final part of the coursework. In the second part of the coursework you created a parser for the Moopl grammar which, given a syntactically correct Moopl program as input, builds an AST representation of the program. In Part 3 you will develop an interpreter which executes Moopl programs by visiting their AST representations. For this part of the coursework we provide functional code (with limitations, see below) for parsing, building a symbol table, type checking and variable allocation. Marks This part of the coursework is worth 12 of the 30 coursework marks for the Language Processors module. This part of the coursework is marked out of 12. Submission deadline This part of the coursework should be handed in before 5pm on Sunday 9th April 2017. In line with school policy, late submissions will be awarded no marks. Return & Feedback Marks and feedback will be available as soon as possible, certainly on or before Wed 3rd May 2017. Plagiarism If you copy the work of others (either that of fellow students or of a third party), with or without their permission, you will score no marks and further disciplinary action will be taken against you. Group working You will be working in the same groups as for the previous parts of the coursework except where group changes have already been approved. Submission: Submit a zip archive (not a rar file) of all your source code (the src folder of your project). We do not want the other parts of your NetBeans project, only the source code. Note 1: Submissions which do not compile will get zero marks. Note 2: You must not change the names or types of any of the existing packages, classes or public methods. 2 Getting started Download either moopl-interp.zip or moopl-interp.tgz from Moodle and extract all files. Key contents to be aware of: • A fully implemented Moopl parser (also implements a parser for the interpreter command language; see below). • A partially implemented Moopl type checker. • Test harnesses for the type checker and interpreter. • A directory of a few example Moopl programs (see Testing below). • Folder interp containing prototype interpreter code. The type-checker is only partially implemented but a more complete implementation will be provided following Session 6. That version is still not fully complete because it doesn’t support inheritance. Part d) below asks you to remove this restriction. The VarAllocator visitor in the interp package uses a simple implementation which only works for methods in which all parameter and local variable names are different. Part e) below asks you to remove this restriction. The three parts below should be attempted in sequence. When you have completed one part you should make a back-up copy of the work and keep it safe, in case you break it in your attempt at the next part. Be sure to test old functionality as well as new (regression testing). We will not assess multiple versions so, if your attempt at part d) or e) breaks previously working code, you may gain a better mark by submitting the earlier version for assessment. c) [8 marks] The Basic Interpreter: complete the implementation of the Interpreter visitor in the interp package. d) [2 marks] Inheritance: extend the type-checker, variable allocator and interpreter to support inheritance. e) [2 marks] Variable Allocation: extend the variable allocator to fully support blockstructure and lexical scoping, removing the requirement that all parameter and local variable names are different. Aim to minimise the number of local variable slots allocated in a stack frame. Note: variable and parameter names declared at the same scope level are still required to be different from each other (a method cannot have two different parameters called x, for example) and this is enforced by the existing typechecking code. But variables declared in different blocks (even when nested) can have the same name. Exceptions Your interpreter will only ever be run on Moopl code which is type-correct (and free from uninitialised local variables). But it is still possible that the Moopl code contains logical errors which may cause runtime errors (such as null-reference or array-bound errors). Your interpreter should throw a MooplRunTimeException with an appropriate error message in these cases. The only kind of exception your interpreter should ever throw is a MooplRunTimeException. 3 Testing The examples folder does not contain a comprehensive test-suite. You need to invent and run your own tests. The document Moopl compared with Java gives a concise summary of how Moopl programs are supposed to behave. You can (and should) also compare the behaviour of your interpreter with that of the online tool: https://smcse.city.ac.uk/student/sj353/langproc/Moopl.html (Note: the online tool checks for uninitialised local variables. Your implementation is not expected to do this.) To test your work, run the top-level Interpret harness, providing the name of a Moopl source file as a command-line argument. When run on a type-correct Moopl source file, Interpret will pretty-print the Moopl program then display a command prompt (>) at which you can enter one of the following commands: :quit This will quit the interpreter. :call main() This will call the top-level proc main, interpreted in the context defined by the Moopl program. (Any top-level proc can be called this way). :eval Exp ; This will evaluate expression Exp, interpreted in the context defined by the Moopl program, and print the result. Note the required terminating semi-colon. Testing your Expression visitors To unit-test your Exp visit methods, run the top-level Interpret harness on a complete Moopl program (though it can be trivial) and use the :eval command. For example, to test your visit methods for the Boolean-literals (ExpTrue and ExpFalse), you would enter the commands > :eval true ; > :eval false ; which should output 1 and 0, respectively. For the most basic cases, the Moopl program is essentially irrelevant (a single top-level proc with empty body may be sufficient). For other cases you will need to write programs containing class definitions (in order, for example, to test object creation and method call). Testing your Statement visitors To unit-test your Stm visit methods, write very simple Moopl programs, each with a top-level proc main() containing just a few lines of code. Run the top-level Interpret harness on these simple programs and enter the command > :call main() You will find a few examples to get you started in the folder examples/unittests. As for the Exp tests, simple cases can be tested using Moopl programs with just a main proc but for the more complex tests you will need to write Moopl programs containing class definitions. 4 Grading criteria Solutions will be graded according to their functional correctness, and the elegance of their implementation. Below are criteria that guide the award of marks. 70 – 100 [1st class] Work that meets all the requirements in full, constructed and presented to a professional standard. Showing evidence of independent reading, thinking and analysis. 60 – 69 [2:1] Work that makes a good attempt to address the requirements, realising all to some extent and most well. Well-structured and well presented. 50 – 59 [2:2] Work that attempts to address requirements realising all to some extent and some well but perhaps also including irrelevant or underdeveloped material. Structure and presentation may not always be clear. 40 – 49 [3rd class] Work that attempts to address the requirements but only realises them to some extent and may not include important elements or be completely accurate. Structure and presentation may lack clarity. 0 – 39 [fail] Unsatisfactory work that does not adequately address the requirements. Structure and presentation may be confused or incoherent.

1 IN2009: Language Processors Coursework Part 3: The Interpreter Introduction This is the 3rd and final part of the coursework. In the second part of the coursework you created a parser for the Moopl grammar which, given a syntactically correct Moopl program as input, builds an AST representation of the program. In Part 3 you will develop an interpreter which executes Moopl programs by visiting their AST representations. For this part of the coursework we provide functional code (with limitations, see below) for parsing, building a symbol table, type checking and variable allocation. Marks This part of the coursework is worth 12 of the 30 coursework marks for the Language Processors module. This part of the coursework is marked out of 12. Submission deadline This part of the coursework should be handed in before 5pm on Sunday 9th April 2017. In line with school policy, late submissions will be awarded no marks. Return & Feedback Marks and feedback will be available as soon as possible, certainly on or before Wed 3rd May 2017. Plagiarism If you copy the work of others (either that of fellow students or of a third party), with or without their permission, you will score no marks and further disciplinary action will be taken against you. Group working You will be working in the same groups as for the previous parts of the coursework except where group changes have already been approved. Submission: Submit a zip archive (not a rar file) of all your source code (the src folder of your project). We do not want the other parts of your NetBeans project, only the source code. Note 1: Submissions which do not compile will get zero marks. Note 2: You must not change the names or types of any of the existing packages, classes or public methods. 2 Getting started Download either moopl-interp.zip or moopl-interp.tgz from Moodle and extract all files. Key contents to be aware of: • A fully implemented Moopl parser (also implements a parser for the interpreter command language; see below). • A partially implemented Moopl type checker. • Test harnesses for the type checker and interpreter. • A directory of a few example Moopl programs (see Testing below). • Folder interp containing prototype interpreter code. The type-checker is only partially implemented but a more complete implementation will be provided following Session 6. That version is still not fully complete because it doesn’t support inheritance. Part d) below asks you to remove this restriction. The VarAllocator visitor in the interp package uses a simple implementation which only works for methods in which all parameter and local variable names are different. Part e) below asks you to remove this restriction. The three parts below should be attempted in sequence. When you have completed one part you should make a back-up copy of the work and keep it safe, in case you break it in your attempt at the next part. Be sure to test old functionality as well as new (regression testing). We will not assess multiple versions so, if your attempt at part d) or e) breaks previously working code, you may gain a better mark by submitting the earlier version for assessment. c) [8 marks] The Basic Interpreter: complete the implementation of the Interpreter visitor in the interp package. d) [2 marks] Inheritance: extend the type-checker, variable allocator and interpreter to support inheritance. e) [2 marks] Variable Allocation: extend the variable allocator to fully support blockstructure and lexical scoping, removing the requirement that all parameter and local variable names are different. Aim to minimise the number of local variable slots allocated in a stack frame. Note: variable and parameter names declared at the same scope level are still required to be different from each other (a method cannot have two different parameters called x, for example) and this is enforced by the existing typechecking code. But variables declared in different blocks (even when nested) can have the same name. Exceptions Your interpreter will only ever be run on Moopl code which is type-correct (and free from uninitialised local variables). But it is still possible that the Moopl code contains logical errors which may cause runtime errors (such as null-reference or array-bound errors). Your interpreter should throw a MooplRunTimeException with an appropriate error message in these cases. The only kind of exception your interpreter should ever throw is a MooplRunTimeException. 3 Testing The examples folder does not contain a comprehensive test-suite. You need to invent and run your own tests. The document Moopl compared with Java gives a concise summary of how Moopl programs are supposed to behave. You can (and should) also compare the behaviour of your interpreter with that of the online tool: https://smcse.city.ac.uk/student/sj353/langproc/Moopl.html (Note: the online tool checks for uninitialised local variables. Your implementation is not expected to do this.) To test your work, run the top-level Interpret harness, providing the name of a Moopl source file as a command-line argument. When run on a type-correct Moopl source file, Interpret will pretty-print the Moopl program then display a command prompt (>) at which you can enter one of the following commands: :quit This will quit the interpreter. :call main() This will call the top-level proc main, interpreted in the context defined by the Moopl program. (Any top-level proc can be called this way). :eval Exp ; This will evaluate expression Exp, interpreted in the context defined by the Moopl program, and print the result. Note the required terminating semi-colon. Testing your Expression visitors To unit-test your Exp visit methods, run the top-level Interpret harness on a complete Moopl program (though it can be trivial) and use the :eval command. For example, to test your visit methods for the Boolean-literals (ExpTrue and ExpFalse), you would enter the commands > :eval true ; > :eval false ; which should output 1 and 0, respectively. For the most basic cases, the Moopl program is essentially irrelevant (a single top-level proc with empty body may be sufficient). For other cases you will need to write programs containing class definitions (in order, for example, to test object creation and method call). Testing your Statement visitors To unit-test your Stm visit methods, write very simple Moopl programs, each with a top-level proc main() containing just a few lines of code. Run the top-level Interpret harness on these simple programs and enter the command > :call main() You will find a few examples to get you started in the folder examples/unittests. As for the Exp tests, simple cases can be tested using Moopl programs with just a main proc but for the more complex tests you will need to write Moopl programs containing class definitions. 4 Grading criteria Solutions will be graded according to their functional correctness, and the elegance of their implementation. Below are criteria that guide the award of marks. 70 – 100 [1st class] Work that meets all the requirements in full, constructed and presented to a professional standard. Showing evidence of independent reading, thinking and analysis. 60 – 69 [2:1] Work that makes a good attempt to address the requirements, realising all to some extent and most well. Well-structured and well presented. 50 – 59 [2:2] Work that attempts to address requirements realising all to some extent and some well but perhaps also including irrelevant or underdeveloped material. Structure and presentation may not always be clear. 40 – 49 [3rd class] Work that attempts to address the requirements but only realises them to some extent and may not include important elements or be completely accurate. Structure and presentation may lack clarity. 0 – 39 [fail] Unsatisfactory work that does not adequately address the requirements. Structure and presentation may be confused or incoherent.

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Lab Description: Follow the instructions in the lab tasks below to complete Problems 1 through 4. These problems will guide you in observing signal delays and timing hazards of logic circuits (both Sum-of-Products (SOP) and Product-of-Sums (POS) circuits). These problems will also guide you in adding circuitry to eliminate a timing hazard. Use VHDL to design the circuits. Carefully follow the directions provided in the lab tasks below. Write your answers to the questions asked by the problems. Do not print out the VHDL code and waveforms as asked by the problems, instead include these on the cover sheet for this lab and print this out when you are done. Do not worry about annotating or putting arrows/notes on the waveforms–just make sure any signals or transitions of interest are shown in your screenshot. For each problem, use VHDL assignment statements for each gate of the Boolean expression. You must add delay for each gate and inverter as described by the problem. Do this by using the “after” statement: Z <= (A and B) after 1 ns; Refer to Digilent Real Digital Module 8 for more information about the "after" statement. Lab Tasks: 1. Complete Problem 1 of Project 8. Simulate all input combinations for this SOP (Sum-of-Products) expression. However, be aware that specific input sequences are required to observe a timing hazard. The problem states that you will need to observe the output when B and C are both high (logic 1) and A transitions from high to low to high (logic 1 to 0, then back to 1). 2. Complete Problem 4 of Project 8. Increase the delay of the OR gate as specified and re-simulate to answer the questions. 3. Complete Problem 2 of Project 8. Change the delay of the OR gate back to the 1 ns that you used for Problem 1. Add the new logic gate (with delay) to your VHDL for the SOP expression and re-simulate to answer the questions. 4. Complete Problem 3 of Project 8. You may create any POS (Product-of-Sums) expression for this problem, however, not all POS expressions will have a timing hazard (so spend some time thinking about how a timing hazard can be generated with a POS expression). Once again, simulate all input combinations for your POS expression but be aware that specific input sequences are required to observe a timing hazard. For this problem, you will also add the new logic gate (with delay) to your VHDL for your POS expression in order to eliminate the timing hazard; you will need to re-simulate with this additional logic gate in order to answer the questions. Problem 1. Implement the function Y = A’.B + A.C in the VHDL tool. Define the INV, OR and two AND operations separately, and give each operation a 1ns delay. Simulate the circuit with all possible combinations of inputs. Watch all circuit nets (inputs, outputs, and intermediate nets) during the simulation. Answer the questions below. Observe the outputs of the AND gates and the overall circuit output when B and C are both high, and A transitions from H to L and then from L to H (you may want to create another simulation to focus on this behavior). What output behavior do you notice when A transitions? What happens when A transitions and B or C are held a ‘0’? How long is the output glitch? _______ Is it positive ( ) or negative ( ) (circle one)? Change the delay through the inverter to 2ns, and resimulate. Now how long is output glitch? ______ What can you say about the relationship between the inverter gate delay and the length of the timing glitch? Based on this simple experiment, an SOP circuit can exhibit positive/negative glitches (circle one) when an input that arrives at one AND gate in a complemented form and another AND gate in uncomplemented form transitions from a _____ to a _____. Problem 2. Enter the logic equation from problem 1 in the K-map below, and loop the equation with redundant term included. Add the redundant term to the Xilinx circuit, re-simulate, and answer the questions. B C A 00 01 11 10 0 1 F Did adding the new gate to the circuit change the logical behavior of the circuit? What effect did the new gate have on the output, particularly when A changes and B and C are both held high? Problem 3. Create a three-input POS circuit to illustrate the formation of a glitch. Drive the simulator to illustrate a glitch in the POS circuit, and answer the questions below. A POS circuit can exhibit a positive/negative glitch (circle one) when an input that arrives at one OR gate in a complemented form and another OR gate in un-complemented form transitions from a _____ to a _____. Write the POS equation you used to show the glitch: Enter the equation in the K-map below, loop the original equation with the redundant term, add the redundant gate to your Xilinx circuit, and resimulate. How did adding the new gate to the circuit change the logical behavior of the circuit? What effect did the new gate have on the output, particularly when A changes and B and C are both held high? Print and submit the circuits and simulation output, label the output glitches in the simulation output, and draw arrows on the simulation output between the events that caused the glitches (i.e., a transition in an input signal) and the glitches themselves. Problem 4. Copy the SOP circuit above to a new VHDL file, and increase the delay of the output OR gate. Simulate the circuit and answer the questions below. How did adding delay to the output gate change the output transition? Does adding delay to the output gate change the circuit’s glitch behavior in any way? Name: Signal Delays Date: Designing with VHDL Grade Item Grade Five segments of VHDL Code for Problems 1-4: /10 Five simulation screenshots for Problems 1-4: /10 Questions from Problems 1-4: /16 Total Grade: /36 VHDL Code: Copy-paste your VHDL design code (just the code you wrote) for: • The SOP expression with the timing hazard (Problem 1, Project 8): • The SOP expression with increased OR gate delay (Problem 4, Project 8): • The SOP expression with the extra logic gate in order to eliminate the timing hazard (Problem 2, Project 8): • Your POS expression with the timing hazard (Problem 3, Project 8): • Your POS expression with the extra logic gate in order to eliminate the timing hazard (Problem 3, Project 8): Simulation Screenshots: Use the “Print Screen” button to capture your screenshot (it should show the entire screen, not just the window of the program). • The SOP expression with the timing hazard (Problem 1, Project 8): • The SOP expression with increased OR gate delay (Problem 4, Project 8): • The SOP expression with the extra logic gate in order to eliminate the timing hazard (Problem 2, Project 8): • Your POS expression with the timing hazard (Problem 3, Project 8): • Your POS expression with the extra logic gate in order to eliminate the timing hazard (Problem 3, Project 8): Simulation Screenshot Tips: (you can delete this once you capture your screenshot) 1. Make the “Wave” window large by clicking the “+” button near the upper-right of the window 2. Click the “Zoom Full” button (looks like a blue/green-filled magnifying glass) to enlarge your waveforms 3. In order to not print a lot of black, change the color scheme of the “Wave” window: 3.1. Click ToolsEdit Preferences… 3.2. The “By Window” tab should be selected, then click Wave Windows in the “Window List” to the left 3.3. Scroll to the bottom of the “Wave Windows Color Scheme” list and click waveBackground. Then click white in the color “Palette” at the right of the screen. 3.4. Now color the waveforms and text black: 3.4.1. Click LOGIC_0 in the “Wave Windows Color Scheme.” Then click black in the color “Palette” at the right of the screen. 3.4.2. Repeat this for LOGIC_1, timeColor, and cursorColor (if you have a cursor you want to print) 3.5. Once you have captured your screenshot, you can click the Reset Defaults button to restore the “Wave” window to its original color scheme Questions: (Please use this cover sheet to type and print your responses) 1. List the references you used for this lab assignment (e.g. sources/websites used or students with whom you discussed this assignment) 2. Do you have any comments or suggestions for this lab exercise?

Lab Description: Follow the instructions in the lab tasks below to complete Problems 1 through 4. These problems will guide you in observing signal delays and timing hazards of logic circuits (both Sum-of-Products (SOP) and Product-of-Sums (POS) circuits). These problems will also guide you in adding circuitry to eliminate a timing hazard. Use VHDL to design the circuits. Carefully follow the directions provided in the lab tasks below. Write your answers to the questions asked by the problems. Do not print out the VHDL code and waveforms as asked by the problems, instead include these on the cover sheet for this lab and print this out when you are done. Do not worry about annotating or putting arrows/notes on the waveforms–just make sure any signals or transitions of interest are shown in your screenshot. For each problem, use VHDL assignment statements for each gate of the Boolean expression. You must add delay for each gate and inverter as described by the problem. Do this by using the “after” statement: Z <= (A and B) after 1 ns; Refer to Digilent Real Digital Module 8 for more information about the "after" statement. Lab Tasks: 1. Complete Problem 1 of Project 8. Simulate all input combinations for this SOP (Sum-of-Products) expression. However, be aware that specific input sequences are required to observe a timing hazard. The problem states that you will need to observe the output when B and C are both high (logic 1) and A transitions from high to low to high (logic 1 to 0, then back to 1). 2. Complete Problem 4 of Project 8. Increase the delay of the OR gate as specified and re-simulate to answer the questions. 3. Complete Problem 2 of Project 8. Change the delay of the OR gate back to the 1 ns that you used for Problem 1. Add the new logic gate (with delay) to your VHDL for the SOP expression and re-simulate to answer the questions. 4. Complete Problem 3 of Project 8. You may create any POS (Product-of-Sums) expression for this problem, however, not all POS expressions will have a timing hazard (so spend some time thinking about how a timing hazard can be generated with a POS expression). Once again, simulate all input combinations for your POS expression but be aware that specific input sequences are required to observe a timing hazard. For this problem, you will also add the new logic gate (with delay) to your VHDL for your POS expression in order to eliminate the timing hazard; you will need to re-simulate with this additional logic gate in order to answer the questions. Problem 1. Implement the function Y = A’.B + A.C in the VHDL tool. Define the INV, OR and two AND operations separately, and give each operation a 1ns delay. Simulate the circuit with all possible combinations of inputs. Watch all circuit nets (inputs, outputs, and intermediate nets) during the simulation. Answer the questions below. Observe the outputs of the AND gates and the overall circuit output when B and C are both high, and A transitions from H to L and then from L to H (you may want to create another simulation to focus on this behavior). What output behavior do you notice when A transitions? What happens when A transitions and B or C are held a ‘0’? How long is the output glitch? _______ Is it positive ( ) or negative ( ) (circle one)? Change the delay through the inverter to 2ns, and resimulate. Now how long is output glitch? ______ What can you say about the relationship between the inverter gate delay and the length of the timing glitch? Based on this simple experiment, an SOP circuit can exhibit positive/negative glitches (circle one) when an input that arrives at one AND gate in a complemented form and another AND gate in uncomplemented form transitions from a _____ to a _____. Problem 2. Enter the logic equation from problem 1 in the K-map below, and loop the equation with redundant term included. Add the redundant term to the Xilinx circuit, re-simulate, and answer the questions. B C A 00 01 11 10 0 1 F Did adding the new gate to the circuit change the logical behavior of the circuit? What effect did the new gate have on the output, particularly when A changes and B and C are both held high? Problem 3. Create a three-input POS circuit to illustrate the formation of a glitch. Drive the simulator to illustrate a glitch in the POS circuit, and answer the questions below. A POS circuit can exhibit a positive/negative glitch (circle one) when an input that arrives at one OR gate in a complemented form and another OR gate in un-complemented form transitions from a _____ to a _____. Write the POS equation you used to show the glitch: Enter the equation in the K-map below, loop the original equation with the redundant term, add the redundant gate to your Xilinx circuit, and resimulate. How did adding the new gate to the circuit change the logical behavior of the circuit? What effect did the new gate have on the output, particularly when A changes and B and C are both held high? Print and submit the circuits and simulation output, label the output glitches in the simulation output, and draw arrows on the simulation output between the events that caused the glitches (i.e., a transition in an input signal) and the glitches themselves. Problem 4. Copy the SOP circuit above to a new VHDL file, and increase the delay of the output OR gate. Simulate the circuit and answer the questions below. How did adding delay to the output gate change the output transition? Does adding delay to the output gate change the circuit’s glitch behavior in any way? Name: Signal Delays Date: Designing with VHDL Grade Item Grade Five segments of VHDL Code for Problems 1-4: /10 Five simulation screenshots for Problems 1-4: /10 Questions from Problems 1-4: /16 Total Grade: /36 VHDL Code: Copy-paste your VHDL design code (just the code you wrote) for: • The SOP expression with the timing hazard (Problem 1, Project 8): • The SOP expression with increased OR gate delay (Problem 4, Project 8): • The SOP expression with the extra logic gate in order to eliminate the timing hazard (Problem 2, Project 8): • Your POS expression with the timing hazard (Problem 3, Project 8): • Your POS expression with the extra logic gate in order to eliminate the timing hazard (Problem 3, Project 8): Simulation Screenshots: Use the “Print Screen” button to capture your screenshot (it should show the entire screen, not just the window of the program). • The SOP expression with the timing hazard (Problem 1, Project 8): • The SOP expression with increased OR gate delay (Problem 4, Project 8): • The SOP expression with the extra logic gate in order to eliminate the timing hazard (Problem 2, Project 8): • Your POS expression with the timing hazard (Problem 3, Project 8): • Your POS expression with the extra logic gate in order to eliminate the timing hazard (Problem 3, Project 8): Simulation Screenshot Tips: (you can delete this once you capture your screenshot) 1. Make the “Wave” window large by clicking the “+” button near the upper-right of the window 2. Click the “Zoom Full” button (looks like a blue/green-filled magnifying glass) to enlarge your waveforms 3. In order to not print a lot of black, change the color scheme of the “Wave” window: 3.1. Click ToolsEdit Preferences… 3.2. The “By Window” tab should be selected, then click Wave Windows in the “Window List” to the left 3.3. Scroll to the bottom of the “Wave Windows Color Scheme” list and click waveBackground. Then click white in the color “Palette” at the right of the screen. 3.4. Now color the waveforms and text black: 3.4.1. Click LOGIC_0 in the “Wave Windows Color Scheme.” Then click black in the color “Palette” at the right of the screen. 3.4.2. Repeat this for LOGIC_1, timeColor, and cursorColor (if you have a cursor you want to print) 3.5. Once you have captured your screenshot, you can click the Reset Defaults button to restore the “Wave” window to its original color scheme Questions: (Please use this cover sheet to type and print your responses) 1. List the references you used for this lab assignment (e.g. sources/websites used or students with whom you discussed this assignment) 2. Do you have any comments or suggestions for this lab exercise?

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Develop a 4 page-500 word précis on Chapter 7 “How to Monitor & Control a TPM Project” of the Wysocki 7th Ed. text.”

Develop a 4 page-500 word précis on Chapter 7 “How to Monitor & Control a TPM Project” of the Wysocki 7th Ed. text.”

Summary of ‘How to Monitor and Control a TPM Project’ … Read More...
Lab Description: Follow the instructions in the lab tasks below to behaviorially create and simulate a flip-flop. Afterwards, you will create a register and Arithmetic Logic Unit (ALU). Refer to Module 7 from the Digilent Real Digital website for more information about ALUs. These two components are the main components required to create an accumulator datapath. This accumulator datapath will act like a simple processor; the ALU will execute simple arithmetic/logic operations and each result will be stored in the register. In an accumulator, the value of the register will be upedated with each operation; the register is used as an input to the ALU and the newly computed result of the operation will be stored back into the register. You will create and implement this accumulator datapath in the last task of this lab. However, you will need to add an additional component to enable it to clearly operate on the FPGA board. You will create and use a clock divider to create a slower version of the FPGA board’s clock when you implement the accumulator datapath on the FPGA board. Refer to Module 10 from the Digilent Real Digital website for more information about clock dividers. Lab Tasks: 1. Create a behavioral VHDL module for a Rising-Edge Triggered (RET) D-Flip-Flop (DFF): a. In your design, use inputs “D” (data), “CLK” (the clock), “RST” (an asynchronous reset), “SET” (a synchronous set or preset signal), “CE” (clock enable), and output “Q” b. Create a VHDL test bench and simulate the flip-flop. Be sure to show the following behaviors with your simulation: i. The output “Q” sampling a ‘0’ from the input “D” ii. The output “Q” sampling a ‘1’ from the input “D” iii. The correct operation of the asynchronous reset iv. The correct operation of the synchronous preset v. The correct operation of the clock enable c. Include a screenshot of your simulation on the lab’s cover sheet. Label each of these behaviors on the waveform (it is ok to print out your cover sheet and write each behavior on the waveform). 2. Create a behavioral VHDL module for a 4-bit Arithmetic Logic Unit (ALU): a. I suggest you refer to Module 7 from the Digilent Real Digital website (in particular, the sections about ALU circuits and behavioral VHDL ALU descriptions). This 4-bit ALU will calculate arithmetic and logical expressions on two 4-bit numbers. Use behavioral expressions for the arithmetic and logic expressions (do not use port map statements to create a structural design using your ripple-carry adder from lab 3). Assume that the select input (or opcode) is 2-bits and is defined as shown in the table below: Opcode Function 00 A 01 A plus 1 10 A plus B 11 A and B b. Create a VHDL test bench to test your ALU. Use two input signal (the 4-bit values for A and B) combinations to test each operation of the ALU. Simulate your design and verify your output. Include a screenshot of your simulation on the lab’s cover sheet. 3. Create an accumulator datapath: a. First, create a 4-bit register. This is very similar to your flip-flop design from lab task 1. Ensure that your 4-bit register has inputs “D” (data), “CLK” (the clock), and “RST” (an asynchronous reset), and an output “Q”. Create a test bench and ensure that your 4-bit register operates correctly. b. Next, create a design module for the accumulator datapath and import your 4-bit register, 4-bit ALU, and seven-sgement display decoder (from lab 2) as components to this system. Connect your register, ALU, and seven-segment display decoder as follows: i. Connect the output of your ALU to the “D” input of your register ii. Connect the “Q” output of your register to both the “A” input of your ALU and the input of your seven-segement display iii. You should be left with four overall inputs: the “B” input of your ALU, the opcode input of your ALU, the CLK, and RST iv. You should be left with one overall output: the seven-segment display output c. Create a test bench to simulate the behavior of your accumulator datapath. In your test bench, simulate a few clock cycles to verify the correct operation of your system. d. Before implementing this system on the FPGA board, create and add one additional component to your system. Create and add a clock divider to this system; the input will be the board’s clock and the output will be a slower version of the clock to use for the register. Design your clock divider to slow the clock frequency to 1 Hz (1 clock cycle per second). Note that the clock on the lab FPGA board (Spartan 3) has a frequency of 50 MHz. If you purchased your board, the FPGA Basys 3 or Nexys 4 DDR FPGA board has a frequency of 100 MHz. I highly recommend taking a look at “Binary counters in VHDL” from Module 10 from the Digilent Real Digital website for information about clock dividers. e. Now, implement this system on the FPGA board. Connect the data input to four switches, connect the ALU opcode inputs to two buttons, the RST signal to one button, the CLK signal to the board’s clock, and the seven-segment display output to the seven-segment display. f. Ask the instructor to check your design, simulation waveforms, and FPGA board implementation of your circuit

Lab Description: Follow the instructions in the lab tasks below to behaviorially create and simulate a flip-flop. Afterwards, you will create a register and Arithmetic Logic Unit (ALU). Refer to Module 7 from the Digilent Real Digital website for more information about ALUs. These two components are the main components required to create an accumulator datapath. This accumulator datapath will act like a simple processor; the ALU will execute simple arithmetic/logic operations and each result will be stored in the register. In an accumulator, the value of the register will be upedated with each operation; the register is used as an input to the ALU and the newly computed result of the operation will be stored back into the register. You will create and implement this accumulator datapath in the last task of this lab. However, you will need to add an additional component to enable it to clearly operate on the FPGA board. You will create and use a clock divider to create a slower version of the FPGA board’s clock when you implement the accumulator datapath on the FPGA board. Refer to Module 10 from the Digilent Real Digital website for more information about clock dividers. Lab Tasks: 1. Create a behavioral VHDL module for a Rising-Edge Triggered (RET) D-Flip-Flop (DFF): a. In your design, use inputs “D” (data), “CLK” (the clock), “RST” (an asynchronous reset), “SET” (a synchronous set or preset signal), “CE” (clock enable), and output “Q” b. Create a VHDL test bench and simulate the flip-flop. Be sure to show the following behaviors with your simulation: i. The output “Q” sampling a ‘0’ from the input “D” ii. The output “Q” sampling a ‘1’ from the input “D” iii. The correct operation of the asynchronous reset iv. The correct operation of the synchronous preset v. The correct operation of the clock enable c. Include a screenshot of your simulation on the lab’s cover sheet. Label each of these behaviors on the waveform (it is ok to print out your cover sheet and write each behavior on the waveform). 2. Create a behavioral VHDL module for a 4-bit Arithmetic Logic Unit (ALU): a. I suggest you refer to Module 7 from the Digilent Real Digital website (in particular, the sections about ALU circuits and behavioral VHDL ALU descriptions). This 4-bit ALU will calculate arithmetic and logical expressions on two 4-bit numbers. Use behavioral expressions for the arithmetic and logic expressions (do not use port map statements to create a structural design using your ripple-carry adder from lab 3). Assume that the select input (or opcode) is 2-bits and is defined as shown in the table below: Opcode Function 00 A 01 A plus 1 10 A plus B 11 A and B b. Create a VHDL test bench to test your ALU. Use two input signal (the 4-bit values for A and B) combinations to test each operation of the ALU. Simulate your design and verify your output. Include a screenshot of your simulation on the lab’s cover sheet. 3. Create an accumulator datapath: a. First, create a 4-bit register. This is very similar to your flip-flop design from lab task 1. Ensure that your 4-bit register has inputs “D” (data), “CLK” (the clock), and “RST” (an asynchronous reset), and an output “Q”. Create a test bench and ensure that your 4-bit register operates correctly. b. Next, create a design module for the accumulator datapath and import your 4-bit register, 4-bit ALU, and seven-sgement display decoder (from lab 2) as components to this system. Connect your register, ALU, and seven-segment display decoder as follows: i. Connect the output of your ALU to the “D” input of your register ii. Connect the “Q” output of your register to both the “A” input of your ALU and the input of your seven-segement display iii. You should be left with four overall inputs: the “B” input of your ALU, the opcode input of your ALU, the CLK, and RST iv. You should be left with one overall output: the seven-segment display output c. Create a test bench to simulate the behavior of your accumulator datapath. In your test bench, simulate a few clock cycles to verify the correct operation of your system. d. Before implementing this system on the FPGA board, create and add one additional component to your system. Create and add a clock divider to this system; the input will be the board’s clock and the output will be a slower version of the clock to use for the register. Design your clock divider to slow the clock frequency to 1 Hz (1 clock cycle per second). Note that the clock on the lab FPGA board (Spartan 3) has a frequency of 50 MHz. If you purchased your board, the FPGA Basys 3 or Nexys 4 DDR FPGA board has a frequency of 100 MHz. I highly recommend taking a look at “Binary counters in VHDL” from Module 10 from the Digilent Real Digital website for information about clock dividers. e. Now, implement this system on the FPGA board. Connect the data input to four switches, connect the ALU opcode inputs to two buttons, the RST signal to one button, the CLK signal to the board’s clock, and the seven-segment display output to the seven-segment display. f. Ask the instructor to check your design, simulation waveforms, and FPGA board implementation of your circuit

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. Name a big idea (major concept) in your subject area and write a one paragraph rationale for why students should learn it.

. Name a big idea (major concept) in your subject area and write a one paragraph rationale for why students should learn it.

Mathematics: mathematics is interesting and enjoyable. People like its test, … Read More...