Design an automotive production line by using one of the following simulation software// ARENA/SIMLU8/WITNESS/ShowFlow and SIMIO then write a 2500 words report describing this project.

Design an automotive production line by using one of the following simulation software// ARENA/SIMLU8/WITNESS/ShowFlow and SIMIO then write a 2500 words report describing this project.

Lab Description: Follow the instructions in the lab tasks below to complete Problems 1 through 4. These problems will guide you in observing signal delays and timing hazards of logic circuits (both Sum-of-Products (SOP) and Product-of-Sums (POS) circuits). These problems will also guide you in adding circuitry to eliminate a timing hazard. Use VHDL to design the circuits. Carefully follow the directions provided in the lab tasks below. Write your answers to the questions asked by the problems. Do not print out the VHDL code and waveforms as asked by the problems, instead include these on the cover sheet for this lab and print this out when you are done. Do not worry about annotating or putting arrows/notes on the waveforms–just make sure any signals or transitions of interest are shown in your screenshot. For each problem, use VHDL assignment statements for each gate of the Boolean expression. You must add delay for each gate and inverter as described by the problem. Do this by using the “after” statement: Z <= (A and B) after 1 ns; Refer to Digilent Real Digital Module 8 for more information about the "after" statement. Lab Tasks: 1. Complete Problem 1 of Project 8. Simulate all input combinations for this SOP (Sum-of-Products) expression. However, be aware that specific input sequences are required to observe a timing hazard. The problem states that you will need to observe the output when B and C are both high (logic 1) and A transitions from high to low to high (logic 1 to 0, then back to 1). 2. Complete Problem 4 of Project 8. Increase the delay of the OR gate as specified and re-simulate to answer the questions. 3. Complete Problem 2 of Project 8. Change the delay of the OR gate back to the 1 ns that you used for Problem 1. Add the new logic gate (with delay) to your VHDL for the SOP expression and re-simulate to answer the questions. 4. Complete Problem 3 of Project 8. You may create any POS (Product-of-Sums) expression for this problem, however, not all POS expressions will have a timing hazard (so spend some time thinking about how a timing hazard can be generated with a POS expression). Once again, simulate all input combinations for your POS expression but be aware that specific input sequences are required to observe a timing hazard. For this problem, you will also add the new logic gate (with delay) to your VHDL for your POS expression in order to eliminate the timing hazard; you will need to re-simulate with this additional logic gate in order to answer the questions. Problem 1. Implement the function Y = A’.B + A.C in the VHDL tool. Define the INV, OR and two AND operations separately, and give each operation a 1ns delay. Simulate the circuit with all possible combinations of inputs. Watch all circuit nets (inputs, outputs, and intermediate nets) during the simulation. Answer the questions below. Observe the outputs of the AND gates and the overall circuit output when B and C are both high, and A transitions from H to L and then from L to H (you may want to create another simulation to focus on this behavior). What output behavior do you notice when A transitions? What happens when A transitions and B or C are held a ‘0’? How long is the output glitch? _______ Is it positive ( ) or negative ( ) (circle one)? Change the delay through the inverter to 2ns, and resimulate. Now how long is output glitch? ______ What can you say about the relationship between the inverter gate delay and the length of the timing glitch? Based on this simple experiment, an SOP circuit can exhibit positive/negative glitches (circle one) when an input that arrives at one AND gate in a complemented form and another AND gate in uncomplemented form transitions from a _____ to a _____. Problem 2. Enter the logic equation from problem 1 in the K-map below, and loop the equation with redundant term included. Add the redundant term to the Xilinx circuit, re-simulate, and answer the questions. B C A 00 01 11 10 0 1 F Did adding the new gate to the circuit change the logical behavior of the circuit? What effect did the new gate have on the output, particularly when A changes and B and C are both held high? Problem 3. Create a three-input POS circuit to illustrate the formation of a glitch. Drive the simulator to illustrate a glitch in the POS circuit, and answer the questions below. A POS circuit can exhibit a positive/negative glitch (circle one) when an input that arrives at one OR gate in a complemented form and another OR gate in un-complemented form transitions from a _____ to a _____. Write the POS equation you used to show the glitch: Enter the equation in the K-map below, loop the original equation with the redundant term, add the redundant gate to your Xilinx circuit, and resimulate. How did adding the new gate to the circuit change the logical behavior of the circuit? What effect did the new gate have on the output, particularly when A changes and B and C are both held high? Print and submit the circuits and simulation output, label the output glitches in the simulation output, and draw arrows on the simulation output between the events that caused the glitches (i.e., a transition in an input signal) and the glitches themselves. Problem 4. Copy the SOP circuit above to a new VHDL file, and increase the delay of the output OR gate. Simulate the circuit and answer the questions below. How did adding delay to the output gate change the output transition? Does adding delay to the output gate change the circuit’s glitch behavior in any way? Name: Signal Delays Date: Designing with VHDL Grade Item Grade Five segments of VHDL Code for Problems 1-4: /10 Five simulation screenshots for Problems 1-4: /10 Questions from Problems 1-4: /16 Total Grade: /36 VHDL Code: Copy-paste your VHDL design code (just the code you wrote) for: • The SOP expression with the timing hazard (Problem 1, Project 8): • The SOP expression with increased OR gate delay (Problem 4, Project 8): • The SOP expression with the extra logic gate in order to eliminate the timing hazard (Problem 2, Project 8): • Your POS expression with the timing hazard (Problem 3, Project 8): • Your POS expression with the extra logic gate in order to eliminate the timing hazard (Problem 3, Project 8): Simulation Screenshots: Use the “Print Screen” button to capture your screenshot (it should show the entire screen, not just the window of the program). • The SOP expression with the timing hazard (Problem 1, Project 8): • The SOP expression with increased OR gate delay (Problem 4, Project 8): • The SOP expression with the extra logic gate in order to eliminate the timing hazard (Problem 2, Project 8): • Your POS expression with the timing hazard (Problem 3, Project 8): • Your POS expression with the extra logic gate in order to eliminate the timing hazard (Problem 3, Project 8): Simulation Screenshot Tips: (you can delete this once you capture your screenshot) 1. Make the “Wave” window large by clicking the “+” button near the upper-right of the window 2. Click the “Zoom Full” button (looks like a blue/green-filled magnifying glass) to enlarge your waveforms 3. In order to not print a lot of black, change the color scheme of the “Wave” window: 3.1. Click ToolsEdit Preferences… 3.2. The “By Window” tab should be selected, then click Wave Windows in the “Window List” to the left 3.3. Scroll to the bottom of the “Wave Windows Color Scheme” list and click waveBackground. Then click white in the color “Palette” at the right of the screen. 3.4. Now color the waveforms and text black: 3.4.1. Click LOGIC_0 in the “Wave Windows Color Scheme.” Then click black in the color “Palette” at the right of the screen. 3.4.2. Repeat this for LOGIC_1, timeColor, and cursorColor (if you have a cursor you want to print) 3.5. Once you have captured your screenshot, you can click the Reset Defaults button to restore the “Wave” window to its original color scheme Questions: (Please use this cover sheet to type and print your responses) 1. List the references you used for this lab assignment (e.g. sources/websites used or students with whom you discussed this assignment) 2. Do you have any comments or suggestions for this lab exercise?

Lab Description: Follow the instructions in the lab tasks below to complete Problems 1 through 4. These problems will guide you in observing signal delays and timing hazards of logic circuits (both Sum-of-Products (SOP) and Product-of-Sums (POS) circuits). These problems will also guide you in adding circuitry to eliminate a timing hazard. Use VHDL to design the circuits. Carefully follow the directions provided in the lab tasks below. Write your answers to the questions asked by the problems. Do not print out the VHDL code and waveforms as asked by the problems, instead include these on the cover sheet for this lab and print this out when you are done. Do not worry about annotating or putting arrows/notes on the waveforms–just make sure any signals or transitions of interest are shown in your screenshot. For each problem, use VHDL assignment statements for each gate of the Boolean expression. You must add delay for each gate and inverter as described by the problem. Do this by using the “after” statement: Z <= (A and B) after 1 ns; Refer to Digilent Real Digital Module 8 for more information about the "after" statement. Lab Tasks: 1. Complete Problem 1 of Project 8. Simulate all input combinations for this SOP (Sum-of-Products) expression. However, be aware that specific input sequences are required to observe a timing hazard. The problem states that you will need to observe the output when B and C are both high (logic 1) and A transitions from high to low to high (logic 1 to 0, then back to 1). 2. Complete Problem 4 of Project 8. Increase the delay of the OR gate as specified and re-simulate to answer the questions. 3. Complete Problem 2 of Project 8. Change the delay of the OR gate back to the 1 ns that you used for Problem 1. Add the new logic gate (with delay) to your VHDL for the SOP expression and re-simulate to answer the questions. 4. Complete Problem 3 of Project 8. You may create any POS (Product-of-Sums) expression for this problem, however, not all POS expressions will have a timing hazard (so spend some time thinking about how a timing hazard can be generated with a POS expression). Once again, simulate all input combinations for your POS expression but be aware that specific input sequences are required to observe a timing hazard. For this problem, you will also add the new logic gate (with delay) to your VHDL for your POS expression in order to eliminate the timing hazard; you will need to re-simulate with this additional logic gate in order to answer the questions. Problem 1. Implement the function Y = A’.B + A.C in the VHDL tool. Define the INV, OR and two AND operations separately, and give each operation a 1ns delay. Simulate the circuit with all possible combinations of inputs. Watch all circuit nets (inputs, outputs, and intermediate nets) during the simulation. Answer the questions below. Observe the outputs of the AND gates and the overall circuit output when B and C are both high, and A transitions from H to L and then from L to H (you may want to create another simulation to focus on this behavior). What output behavior do you notice when A transitions? What happens when A transitions and B or C are held a ‘0’? How long is the output glitch? _______ Is it positive ( ) or negative ( ) (circle one)? Change the delay through the inverter to 2ns, and resimulate. Now how long is output glitch? ______ What can you say about the relationship between the inverter gate delay and the length of the timing glitch? Based on this simple experiment, an SOP circuit can exhibit positive/negative glitches (circle one) when an input that arrives at one AND gate in a complemented form and another AND gate in uncomplemented form transitions from a _____ to a _____. Problem 2. Enter the logic equation from problem 1 in the K-map below, and loop the equation with redundant term included. Add the redundant term to the Xilinx circuit, re-simulate, and answer the questions. B C A 00 01 11 10 0 1 F Did adding the new gate to the circuit change the logical behavior of the circuit? What effect did the new gate have on the output, particularly when A changes and B and C are both held high? Problem 3. Create a three-input POS circuit to illustrate the formation of a glitch. Drive the simulator to illustrate a glitch in the POS circuit, and answer the questions below. A POS circuit can exhibit a positive/negative glitch (circle one) when an input that arrives at one OR gate in a complemented form and another OR gate in un-complemented form transitions from a _____ to a _____. Write the POS equation you used to show the glitch: Enter the equation in the K-map below, loop the original equation with the redundant term, add the redundant gate to your Xilinx circuit, and resimulate. How did adding the new gate to the circuit change the logical behavior of the circuit? What effect did the new gate have on the output, particularly when A changes and B and C are both held high? Print and submit the circuits and simulation output, label the output glitches in the simulation output, and draw arrows on the simulation output between the events that caused the glitches (i.e., a transition in an input signal) and the glitches themselves. Problem 4. Copy the SOP circuit above to a new VHDL file, and increase the delay of the output OR gate. Simulate the circuit and answer the questions below. How did adding delay to the output gate change the output transition? Does adding delay to the output gate change the circuit’s glitch behavior in any way? Name: Signal Delays Date: Designing with VHDL Grade Item Grade Five segments of VHDL Code for Problems 1-4: /10 Five simulation screenshots for Problems 1-4: /10 Questions from Problems 1-4: /16 Total Grade: /36 VHDL Code: Copy-paste your VHDL design code (just the code you wrote) for: • The SOP expression with the timing hazard (Problem 1, Project 8): • The SOP expression with increased OR gate delay (Problem 4, Project 8): • The SOP expression with the extra logic gate in order to eliminate the timing hazard (Problem 2, Project 8): • Your POS expression with the timing hazard (Problem 3, Project 8): • Your POS expression with the extra logic gate in order to eliminate the timing hazard (Problem 3, Project 8): Simulation Screenshots: Use the “Print Screen” button to capture your screenshot (it should show the entire screen, not just the window of the program). • The SOP expression with the timing hazard (Problem 1, Project 8): • The SOP expression with increased OR gate delay (Problem 4, Project 8): • The SOP expression with the extra logic gate in order to eliminate the timing hazard (Problem 2, Project 8): • Your POS expression with the timing hazard (Problem 3, Project 8): • Your POS expression with the extra logic gate in order to eliminate the timing hazard (Problem 3, Project 8): Simulation Screenshot Tips: (you can delete this once you capture your screenshot) 1. Make the “Wave” window large by clicking the “+” button near the upper-right of the window 2. Click the “Zoom Full” button (looks like a blue/green-filled magnifying glass) to enlarge your waveforms 3. In order to not print a lot of black, change the color scheme of the “Wave” window: 3.1. Click ToolsEdit Preferences… 3.2. The “By Window” tab should be selected, then click Wave Windows in the “Window List” to the left 3.3. Scroll to the bottom of the “Wave Windows Color Scheme” list and click waveBackground. Then click white in the color “Palette” at the right of the screen. 3.4. Now color the waveforms and text black: 3.4.1. Click LOGIC_0 in the “Wave Windows Color Scheme.” Then click black in the color “Palette” at the right of the screen. 3.4.2. Repeat this for LOGIC_1, timeColor, and cursorColor (if you have a cursor you want to print) 3.5. Once you have captured your screenshot, you can click the Reset Defaults button to restore the “Wave” window to its original color scheme Questions: (Please use this cover sheet to type and print your responses) 1. List the references you used for this lab assignment (e.g. sources/websites used or students with whom you discussed this assignment) 2. Do you have any comments or suggestions for this lab exercise?

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7. What are the major considerations regarding logistics alliances, for: a) initiation? b) Implementation? c) Maintenance? d) Termination?

7. What are the major considerations regarding logistics alliances, for: a) initiation? b) Implementation? c) Maintenance? d) Termination?

In addition to running the internal organization, supply chain executives … Read More...
Reflect critically on your learning against aims and objectives. Include a log & evaluation detailing the use of your time on development.

Reflect critically on your learning against aims and objectives. Include a log & evaluation detailing the use of your time on development.

Aims, objectives and learning outcomes provide a clear indication of … Read More...
CURR 5702 Guidelines for Writing Analysis Project 1. Find a piece of writing written by a learner with special needs or an English learner. In your write-up, describe the learner’s background in as much detail as you can (country/language of origin, age/grade, gender, length of time in U.S., educational background, level of proficiency, etc.) and the type of writing it is (journal entry, 5-paragraph essay assignment, free write, etc.). 2. Determine what aspects of language are present in the writing. a. Where is the learner strong? b. Where does he/she need help? c. What features do you notice? (this is a list to get you thinking…you do not need to address every one) i. lexical variety ii. syntactic complexity iii. control of grammatical features (nouns, verbs, preps, etc.) iv. linking features (conjunctions) v. structures that mark order (first, second, later, finally) vi. structures that reference prior elements (using the right pronouns to refer back to some person or thing already mentioned) vii. Others? 3. Consider how you might assess this writing and provide feedback to the learner. a. Will you use a rubric? b. What will you focus on? Here are some possibilities: i. Organization and content ii. Language 1. Sentence fluency 2. Grammar/spelling/word choice iii. All of the above c. How will you convey your feedback? i. In writing 1. Highlight errors 2. Choose a few of the most common errors to highlight/ have the learner correct them? (e.g. Error log) 3. Provide general feedback without marking the paper? ii. Have a conference with the learner and discuss some of the areas in need of revision d. What are the next steps in the process? 4. What are your recommendations for literacy instruction? a. Based on your analysis and connections, how might you address the needs of this learner as a teacher? This is where you can connect your project with your readings from the course (or other readings as appropriate). i. Are there strategies, activities, tools, technology, resources, etc., that would be beneficial for your learner? Describe them and be sure to cite your sources. ii. Directly link the recommendations with the observations that you made in their writing sample and with your readings. 5. Write up the writing analysis you have done. Be sure to include the writing sample as an appendix. If you reference a rubric or Error log, etc., please include that as well. You should incorporate at least 4 references into this project (you can start with the 2 course texts if you like). Be sure to cite your sources within your paper and include a list of references at the end in APA format. The evaluation rubric for this project can be found below. Rubric for Writing Analysis Performance Excellent Good Needs Improvement Unacceptable 5 points 3-4 points 1-2 points 0 points Introduction and Context Writer introduces learner and gives clear context of learner. Writer identifies learner, but does not give full context OR writer describes context, but learner information sketchy. Writer has very little information about learner and/or context. No context provided. Writing Sample Writer describes clearly writing sample. Writer is too general about how writing sample. Writer has provided very little information about sample. No information provided regarding sample or no sample provided. 13-15 points 9-12 points 4-8 points 0-3 points Identification of Writing Challenges Language challenges are clearly identified and samples given to support challenges (including transcript numbers). Clear connections made to relevant topics covered in course. Writer indicates some idea of language challenges. Some support given. Some connections made to relevant topics covered in course. Writer discusses language challenges in general; does not support in terms of transcription. Minimal effort to make connections to relevant topics covered in course. Very little or no discussion language challenges identified and little or no transcription support provided. No connections to course topics. Plan for Assessment and Feedback Clear plan for assessing writing and providing feedback to learner. General plan for assessment; feedback addressed, but more details needed. Plan for assessment not clear; feedback to learner addressed superficially. No plan for assessment or feedback. Recommendations for Instruction Recommendations for instruction are clear and well-supported. Recommendations present, but need more description and support. Recommendations are implied or only partially supported. No recommendations given. 5 points 3-4 points 1-2 points 0 points References Writer includes at least 4 credible sources. Writer includes 3 sources. Writer includes 1-2 resources. Sources not included. Writing Conventions Writing is clear. No grammatical, spelling, or punctuation errors. APA format is correct. A few grammatical, spelling, or punctuation errors. APA format is mostly correct. Some grammatical, spelling, or punctuation errors. Numerous issues with APA format. Many grammatical, spelling, or punctuation errors. APA format disregarded. Total ____ / 75 Comments:

CURR 5702 Guidelines for Writing Analysis Project 1. Find a piece of writing written by a learner with special needs or an English learner. In your write-up, describe the learner’s background in as much detail as you can (country/language of origin, age/grade, gender, length of time in U.S., educational background, level of proficiency, etc.) and the type of writing it is (journal entry, 5-paragraph essay assignment, free write, etc.). 2. Determine what aspects of language are present in the writing. a. Where is the learner strong? b. Where does he/she need help? c. What features do you notice? (this is a list to get you thinking…you do not need to address every one) i. lexical variety ii. syntactic complexity iii. control of grammatical features (nouns, verbs, preps, etc.) iv. linking features (conjunctions) v. structures that mark order (first, second, later, finally) vi. structures that reference prior elements (using the right pronouns to refer back to some person or thing already mentioned) vii. Others? 3. Consider how you might assess this writing and provide feedback to the learner. a. Will you use a rubric? b. What will you focus on? Here are some possibilities: i. Organization and content ii. Language 1. Sentence fluency 2. Grammar/spelling/word choice iii. All of the above c. How will you convey your feedback? i. In writing 1. Highlight errors 2. Choose a few of the most common errors to highlight/ have the learner correct them? (e.g. Error log) 3. Provide general feedback without marking the paper? ii. Have a conference with the learner and discuss some of the areas in need of revision d. What are the next steps in the process? 4. What are your recommendations for literacy instruction? a. Based on your analysis and connections, how might you address the needs of this learner as a teacher? This is where you can connect your project with your readings from the course (or other readings as appropriate). i. Are there strategies, activities, tools, technology, resources, etc., that would be beneficial for your learner? Describe them and be sure to cite your sources. ii. Directly link the recommendations with the observations that you made in their writing sample and with your readings. 5. Write up the writing analysis you have done. Be sure to include the writing sample as an appendix. If you reference a rubric or Error log, etc., please include that as well. You should incorporate at least 4 references into this project (you can start with the 2 course texts if you like). Be sure to cite your sources within your paper and include a list of references at the end in APA format. The evaluation rubric for this project can be found below. Rubric for Writing Analysis Performance Excellent Good Needs Improvement Unacceptable 5 points 3-4 points 1-2 points 0 points Introduction and Context Writer introduces learner and gives clear context of learner. Writer identifies learner, but does not give full context OR writer describes context, but learner information sketchy. Writer has very little information about learner and/or context. No context provided. Writing Sample Writer describes clearly writing sample. Writer is too general about how writing sample. Writer has provided very little information about sample. No information provided regarding sample or no sample provided. 13-15 points 9-12 points 4-8 points 0-3 points Identification of Writing Challenges Language challenges are clearly identified and samples given to support challenges (including transcript numbers). Clear connections made to relevant topics covered in course. Writer indicates some idea of language challenges. Some support given. Some connections made to relevant topics covered in course. Writer discusses language challenges in general; does not support in terms of transcription. Minimal effort to make connections to relevant topics covered in course. Very little or no discussion language challenges identified and little or no transcription support provided. No connections to course topics. Plan for Assessment and Feedback Clear plan for assessing writing and providing feedback to learner. General plan for assessment; feedback addressed, but more details needed. Plan for assessment not clear; feedback to learner addressed superficially. No plan for assessment or feedback. Recommendations for Instruction Recommendations for instruction are clear and well-supported. Recommendations present, but need more description and support. Recommendations are implied or only partially supported. No recommendations given. 5 points 3-4 points 1-2 points 0 points References Writer includes at least 4 credible sources. Writer includes 3 sources. Writer includes 1-2 resources. Sources not included. Writing Conventions Writing is clear. No grammatical, spelling, or punctuation errors. APA format is correct. A few grammatical, spelling, or punctuation errors. APA format is mostly correct. Some grammatical, spelling, or punctuation errors. Numerous issues with APA format. Many grammatical, spelling, or punctuation errors. APA format disregarded. Total ____ / 75 Comments:

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ME4575/5575 Renewable and Alternative Energy Fall 2015 Project 1 In this project, you will design a two piston Stirling engine (as in the example given in the class) of 1 kW power. The engine will be operated at TH=650 0C. The waste energy will be rejected at the temperature of TC=40 0C. The objective of the design is to maximize the efficiency and minimize the system weight. For the given temperature ratio, you have to select and optimize the piston diameter and piston stroke. The weight is proximately equal to the hot and cold piston volume multiplying by steel density. You can use Excel spreadsheet (or other engineering software) to create a Stirling modeling file to iterate on the piston diameter and stroke until the best combination of efficiency and weight (cost) is achieved. The project report has to contain a short introduction, technical description of the problem, details of analyses, and final conclusion of the design (size, weight, and efficiency).

ME4575/5575 Renewable and Alternative Energy Fall 2015 Project 1 In this project, you will design a two piston Stirling engine (as in the example given in the class) of 1 kW power. The engine will be operated at TH=650 0C. The waste energy will be rejected at the temperature of TC=40 0C. The objective of the design is to maximize the efficiency and minimize the system weight. For the given temperature ratio, you have to select and optimize the piston diameter and piston stroke. The weight is proximately equal to the hot and cold piston volume multiplying by steel density. You can use Excel spreadsheet (or other engineering software) to create a Stirling modeling file to iterate on the piston diameter and stroke until the best combination of efficiency and weight (cost) is achieved. The project report has to contain a short introduction, technical description of the problem, details of analyses, and final conclusion of the design (size, weight, and efficiency).