## EE214 Fall 2015 Problem Set1 I am submitting my own work in this exercise, and I am aware of the penalties for cheating that will be assessed if I submit work for credit that is not my own. Print Name Sign Name Date Contains material © Digilent, Inc. 7 pages 1. (15 points) Below are some circuit elements from a simple digital system. 3.3V 20mA VB 1Kohm VA 1.3V RB 1K RC RD SW1 SW2 RA VC When the pushbutton SW1 is not pressed, what is the voltage at VA? (1pt) When the SW1 is pressed, what is the voltage at VA? (1pt) When the SW1 is pressed, what current flows in the 1K resistor RA? (1pt) When SW1 is pressed, what power is dissipated in RA? (2pt) In the LED circuit, 1.3V is required at VB to forward-bias the LED and cause current to flow. Given there is a 1.3V drop across the LED, what resistance RB is required for 20mA to flow through the LED? (2pt) What power is dissipated in the LED? (1pt) In the circuit on the far right, if RC dissipates 25mW, what is VC? (2pt) Using the VC voltage you calculated, if RC is changed to 100Ohms, how much power would it dissipate? (2pt) Using the VC voltage you calculated and a 1K RC, if pressing SW2 causes the total circuit power to increase to 75mW, what value must RD be? (3pt) EE214 Problem Set 1 2. (20 points) Complete the truth tables below. Provide SOP equations for the bottom three tables. F <= Σ ( ) F <= Σ ( ) F <= Σ ( ) 3. (12 points) Write the number of transistors required for each logic gate below inside the gate symbol, and then write the logic gate name below the symbol. 4. (12 points) Complete truth tables for the circuits shown below A B F AND A B F OR A B F XOR A F INV A B C F 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 ? = ? ̅ ∙ ? + ? A B C F 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 ? = ? ∙ ? ∙? ̅ + ? ∙ ? A B C F 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 ? = ? ∙? ̅+? ̅ ∙ ? A B C F 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 A B C F 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 A F B C A B C Y EE214 Problem Set 1 5. (18 points) Show the total transistor count and gate/input number for the circuits below. Then sketch equivalent circuits using NAND gates that use fewer transistors (do not minimize the circuits). 6. (12 points) Sketch circuits for the following logic equations F = A̅ ∙ B ∙ C + A ∙B̅ ∙C̅ +A̅ ∙ C F = A̅ ∙ B ∙C̅ ̅̅̅̅̅̅̅̅̅̅ + ̅A̅̅+̅̅̅B̅ F = (? +? ̅ ) ∙ ̅̅?̅̅̅̅̅+̅̅̅̅̅̅̅?̅̅̅∙̅̅?̅̅ G AB C D AB C D H G F F AB C EE214 Problem Set 1 7. (22 points) Sketch a circuit similar to the figure below that asserts logic 1 only when both switches are closed. Label the switches 1 and 2, and complete the truth table below. Then circle the correct term (high or low, and open or closed) to complete the following sentences describing the AND and OR relationships: AND Relationship: The output F is [high / low] when SW1 is [open / closed], and SW2 is [open / closed]. OR Relationship: The output F is [high / low] when SW1 is [open / closed], or SW2 is [open / closed]. Sketch a circuit similar to the figure below that asserts logic 0 whenever one or both switches are closed. Label the switches 1 and 2, and complete the truth table below. Circle the correct term (high or low, and open or closed) to complete the following sentences describing the AND and OR relationships: AND Relationship: The output F is [high / low] when SW1 is [open / closed], and SW2 is [open / closed]. OR Relationship: The output F is [high / low] when SW1 is [open / closed], or SW2 is [open / closed]. 8. (4 points) Complete the following. A pFET turns [ ON / OFF ] with LLV and conducts [ LHV / LLV ] well (circle one in each bracket). An nFET turns [ ON / OFF ] with LLV and conducts [ LHV / LLV ] well (circle one in each bracket). Vdd GND F SW1 SW2 Vdd GND F SW1 SW2 SW1 SW2 F SW1 SW2 F EE214 Problem Set 1 9. (8 points) Sketch circuits and write Verilog assignment statements for the following equations. F = m(1, 2, 6) F = M(0, 7) 10. (21 points) Complete the truth tables below (enter “on” or “off” under each transistor entry, and “1” or “0” for output F), and enter the gate name and schematic shapes in the tables. You get 1/2 point for each correct column, and 1/2 point each for correct names and shapes. Q1 Q2 Q3 Q4 A B F Vdd Q2 Q1 Q3 Q4 A B F Vdd A B Q1 Q2 Q3 Q4 F 0 0 0 1 1 0 1 1 Gate Name AND shape OR shape A B Q1 Q2 Q3 Q4 F 0 0 0 1 1 0 1 1 Gate Name AND shape OR shape EE214 Problem Set 1 Q2 Q1 Q3 Q4 A B F Q5 Q6 Vdd Q1 Q2 Q3 Q4 A B F Q5 Q6 Vdd (2 points) Enter the logic equation for the 3-input circuit above: A B Q1 Q2 Q3 Q4 F 0 0 0 1 1 0 1 1 Gate Name AND shape OR shape A B Q1 Q2 Q3 Q4 F 0 0 0 1 1 0 1 1 Gate Name AND shape OR shape A B C Q1 Q2 Q3 Q4 Q5 Q6 F 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 F = Q1 Q2 Q4 Q5 A B F Q6 Vdd C Q3 EE214 Problem Set 1 11. (20 points) In a logic function with n inputs, there are 2? unique combinations of inputs and 22? possible logic functions. The table below has four rows that show the four possible combinations of two inputs (22 = 4), and 16 output columns that show all possible two-input logic function (222 = 16). Six of these output columns are associated with common logic functions of two variables. Circle the six columns, and label them with the appropriate logic gate name. Draw the circuit symbols for the functions represented. INPUTS ALL POSSIBLE FUNCTIONS A B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A table like the one above for 3 inputs would need _________ rows and _________ columns. A table like the one above for 4 inputs would need _________ rows and _________ columns. A table like the one above for 5 inputs would need _________ rows and _________ columns. 12. (15 points) Find global minimum circuits for the following three logic signal outputs that are all functions of the same three inputs. Show all work. F1 = m (0, 3, 4) F2 = m (1, 6, 7) F3 = m (0, 1, 3, 4)

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